Multi-Mode Modulation with ZVS for a Single-Phase Single-Stage Inverter

Serrano López, Diego and Ramos Hortal, Regina and Alou Cervera, Pedro and Oliver Ramírez, Jesús Angel and Cobos Marquez, Jose Antonio (2019). Multi-Mode Modulation with ZVS for a Single-Phase Single-Stage Inverter. "IEE Transactions on Power Electronics" (n. 35); pp. 5319-5330. ISSN 0885-8993. https://doi.org/10.1109/TPEL.2019.2941471.

Description

Title: Multi-Mode Modulation with ZVS for a Single-Phase Single-Stage Inverter
Author/s:
  • Serrano López, Diego
  • Ramos Hortal, Regina
  • Alou Cervera, Pedro
  • Oliver Ramírez, Jesús Angel
  • Cobos Marquez, Jose Antonio
Item Type: Article
Título de Revista/Publicación: IEE Transactions on Power Electronics
Date: September 2019
ISSN: 0885-8993
Subjects:
Freetext Keywords: DC-AC power converters; Inverters
Faculty: E.T.S.I. Industriales (UPM)
Department: Automática, Ingeniería Eléctrica y Electrónica e Informática Industrial
Creative Commons Licenses: Recognition - No derivative works - Non commercial

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Abstract

This article presents a modulation with zero-voltage switching (ZVS) for a single-phase, single-stage inverter intended for photovoltaic applications. In single-stage inverters, the dc-ac conversion stage is merged with the active power pulsation buffer stage. The proposed architecture uses a flying capacitor to handle the difference between the instantaneous input and output power, instead of the traditional bulky input capacitor. In this single-stage inverter, both the input current and the output voltage are controlled by the current of a single inductor. The inductor is operated in variable frequency boundary conduction mode. Multiple operation modes are used along the line cycle, all of them with ZVS in all transitions. The operation mode and control times are determined by the target input current, target inductor current, input voltage, output voltage, and flying capacitor voltage through equations that model the inductor waveform. These equations are solved with a fixed-point iteration method in a field-programmable gate array (FPGA). The modulation and control are validated in a 1 kVA prototype with 400 V input and 240 Vrms, 60 Hz output.

More information

Item ID: 63902
DC Identifier: https://oa.upm.es/63902/
OAI Identifier: oai:oa.upm.es:63902
DOI: 10.1109/TPEL.2019.2941471
Official URL: https://ieeexplore.ieee.org/document/8839568
Deposited by: Memoria Investigacion
Deposited on: 19 Jan 2023 09:21
Last Modified: 19 Jan 2023 09:21
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