Design space exploration of heterogeneous MPSoCs with variable number of hardware accelerators

Xu, Siyuan and Liu, Shuangnan and Liu, Yidi and Mahapatra, Anushree and Villaverde San José, Mónica and Moreno González, Félix Antonio and Carrión Schafer, Benjamín (2019). Design space exploration of heterogeneous MPSoCs with variable number of hardware accelerators. "Microprocessors and Microsystems", v. 65 ; pp. 169-179. ISSN 0141-9331. https://doi.org/10.1016/j.micpro.2019.01.010.

Description

Title: Design space exploration of heterogeneous MPSoCs with variable number of hardware accelerators
Author/s:
  • Xu, Siyuan
  • Liu, Shuangnan
  • Liu, Yidi
  • Mahapatra, Anushree
  • Villaverde San José, Mónica
  • Moreno González, Félix Antonio
  • Carrión Schafer, Benjamín
Item Type: Article
Título de Revista/Publicación: Microprocessors and Microsystems
Date: March 2019
ISSN: 0141-9331
Volume: 65
Subjects:
Freetext Keywords: Design space exploration; Heterogeneous SoCs; Hardware accelerators; High-level synthesis; In-situ exploration; Simulation acceleration
Faculty: E.T.S.I. Industriales (UPM)
Department: Ingeniería Mecánica
Creative Commons Licenses: Recognition - No derivative works - Non commercial

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Abstract

This work proposes three different methods to automatically characterize heterogeneous MPSoCs composed of a variable number of masters (in the form of processors) and hardware accelerators (HWaccs). These hardware accelerators are given as Behavioral IPs (BIPs) mapped as loosely coupled accelerators on a shared bus system (i.e. AHB, AXI). BIPs have a distinct advantage over traditional RT-level based IPs given VHDL or Verilog: The ability to generate micro-architectures with different area vs. performance trade-offs from the same description. This is usually done by specifying different synthesis directives in the form of pragmas. This in turn implies that using different mixes of the accelerators’ micro-architectures lead to SoCs with unique area vs. performance trade-offs. Two of the three methods proposed are based on cycle-accurate simulations of the complete MPSoC, while the third method accelerates this exploration by performing it on a Configurable SoC FPGA. Extensive experimental results compare these three methods and highlight their strengths and weaknesses.

More information

Item ID: 66874
DC Identifier: https://oa.upm.es/66874/
OAI Identifier: oai:oa.upm.es:66874
DOI: 10.1016/j.micpro.2019.01.010
Official URL: https://www.sciencedirect.com/science/article/pii/S0141933118302679?via%3Dihub#!
Deposited by: Memoria Investigacion
Deposited on: 29 Apr 2021 16:22
Last Modified: 29 Apr 2021 16:22
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