A Fast Prototyping Workflow for Reconfigurable SDR Applications

García Gener, Alejandro and Valverde, J. and Otero Marnotes, Andres and Harris, Philip J. (2019). A Fast Prototyping Workflow for Reconfigurable SDR Applications. In: "2019 14th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC)", 1-6 Jul 2019, York, UK. ISBN 978-1-7281-4770-3. pp. 66-73. https://doi.org/10.1109/ReCoSoC48741.2019.9034925.

Description

Title: A Fast Prototyping Workflow for Reconfigurable SDR Applications
Author/s:
  • García Gener, Alejandro
  • Valverde, J.
  • Otero Marnotes, Andres
  • Harris, Philip J.
Item Type: Presentation at Congress or Conference (Article)
Event Title: 2019 14th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC)
Event Dates: 1-6 Jul 2019
Event Location: York, UK
Title of Book: 2019 14th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC)
Date: 2019
ISBN: 978-1-7281-4770-3
Subjects:
Freetext Keywords: Model-based design; SDR; FPGA; DP
Faculty: E.T.S.I. Industriales (UPM)
Department: Automática, Ingeniería Eléctrica y Electrónica e Informática Industrial
Creative Commons Licenses: Recognition - No derivative works - Non commercial

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Abstract

Nowadays, the level of complexity attained by embedded systems is convoluting the barrier between simulation and implementation. Dealing with complexity requires of new abstraction layers amongst design phases to guide the process from requirements to implementation. Model-based design methodologies offers an effective alternative to address these designs, but existing commercial tools are limited as new implementation technologies appear. This paper addresses this design problem by proposing an architecture and a methodology for fast prototyping of runtime adaptive Software Defined Radio applications on FPGAs. The methodology follows a model-based design approach including hardware-in-the-loop testing using automatic code generation. The processing architecture has been designed so Dynamic Partial Reconfiguration is possible to switch amongst different processing elements seamlessly at runtime. This approach speeds up the response for test iterations in SDR embedded designs going from hours to ten minutes, which is crucial to save costs.

More information

Item ID: 66945
DC Identifier: https://oa.upm.es/66945/
OAI Identifier: oai:oa.upm.es:66945
DOI: 10.1109/ReCoSoC48741.2019.9034925
Official URL: https://www.recosoc.org/
Deposited by: Memoria Investigacion
Deposited on: 04 May 2021 13:54
Last Modified: 04 May 2021 13:56
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