A 40nm Critical Path Monitor for the Detection of Setup and Hold Time Violations.

Aparicio Cerqueira, Hernán and Ituero Herrero, Pablo (2018). A 40nm Critical Path Monitor for the Detection of Setup and Hold Time Violations.. In: "28th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS)", 02/07/2018 - 04/07/2018, Platja d'Aro, Spain. ISBN 978-1-5386-6365-3. pp. 1-6. https://doi.org/10.1109/PATMOS.2018.8464155.

Description

Title: A 40nm Critical Path Monitor for the Detection of Setup and Hold Time Violations.
Author/s:
  • Aparicio Cerqueira, Hernán
  • Ituero Herrero, Pablo
Item Type: Presentation at Congress or Conference (Article)
Event Title: 28th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS)
Event Dates: 02/07/2018 - 04/07/2018
Event Location: Platja d'Aro, Spain
Title of Book: 28th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS)
Date: 2018
ISBN: 978-1-5386-6365-3
Subjects:
Faculty: E.T.S.I. Telecomunicación (UPM)
Department: Ingeniería Electrónica
Creative Commons Licenses: Recognition - No derivative works - Non commercial

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Abstract

In the current context of strict low-power requirements, complex dynamic frequency and voltage scale systems try to constantly push the operating conditions of electronic chips to the lower bound that fulfills the performance requirements. Also, at test time of a synchronous electronic system, any occurrence of timing violations, especially hold time violations, must be identified, located and corrected. Critical path monitors serve these two purposes, they measure the delays where transients are produced in relation to the clock signal for the critical paths of the system. This work introduces a critical path monitor architecture that yields two configurable digital outputs: one for setup time violations, and another for hold time violations. The monitor directly senses the critical path, without the need to introduce synthesized replicas. The architecture has been validated in a 40nm commercial technology, it takes an area of 4028 um2 and it is very robust against PVT variations.

Funding Projects

TypeCodeAcronymLeaderTitle
Government of SpainTEC2015-65902TOLERA2UnspecifiedVariability in Nanometric technologies: Tolerance, Reliability and Benefits

More information

Item ID: 67241
DC Identifier: https://oa.upm.es/67241/
OAI Identifier: oai:oa.upm.es:67241
DOI: 10.1109/PATMOS.2018.8464155
Official URL: https://ieeexplore.ieee.org/document/8464155
Deposited by: Memoria Investigacion
Deposited on: 12 Jun 2021 09:42
Last Modified: 12 Jun 2021 09:42
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