Full text
|
PDF
- Requires a PDF viewer, such as GSview, Xpdf or Adobe Acrobat Reader
Download (647kB) | Preview |
Design and implementation in a DSP of a digital double voltage/current loop for a power inverter for an aircraft application
Citation
Duret, Benoit Alexandre and Moreno González, Félix Antonio and Meneses Herrera, David and García Suárez, Oscar and Oliver Ramírez, Jesús Angel and Alou Cervera, Pedro and Cobos Márquez, José Antonio (2010). Design and implementation in a DSP of a digital double voltage/current loop for a power inverter for an aircraft application. In: "XXV Conference on Design of Circuits and Integrated Systems, 2010 (DCIS)", 17/11/2010 - 19/11/2010, Lanzarote, Canarias, España.
Description
| Title: | Design and implementation in a DSP of a digital double voltage/current loop for a power inverter for an aircraft application |
|---|---|
| Author/s: |
|
| Item Type: | Presentation at Congress or Conference (Article) |
| Event Title: | XXV Conference on Design of Circuits and Integrated Systems, 2010 (DCIS) |
| Event Dates: | 17/11/2010 - 19/11/2010 |
| Event Location: | Lanzarote, Canarias, España |
| Title of Book: | Proceedings of XXV Conference on Design of Circuits and Integrated Systems, 2010 (DCIS) |
| Date: | 2010 |
| Subjects: | |
| Freetext Keywords: | Digital Signal Processor ; Control Loop design ; Comunication protocol ; Inverter 400H |
| Faculty: | E.T.S.I. Industriales (UPM) |
| Department: | Automática, Ingeniería Electrónica e Informática Industrial [hasta 2014] |
| Creative Commons Licenses: | Recognition - No derivative works - Non commercial |
Abstract
In this paper is presented a method of control of a power inverter with a DSP. The control is based on two PWMs that controlled a full bridge. Being an application for avionics, a slow branch has a frequency of 400Hz. In order to have precision in the final waveform, the fast branch of the full bridge is 40 kHz, what prevents a calculation time of 25µs for the computation for all the system. In addition, a communication protocol has been implemented to be able to put the inverters in a parallel mode and in three phase mode
More information
| Item ID: | 7771 |
|---|---|
| DC Identifier: | https://oa.upm.es/7771/ |
| OAI Identifier: | oai:oa.upm.es:7771 |
| Official URL: | http://www.iuma.ulpgc.es/dcis2010/ |
| Deposited by: | Memoria Investigacion |
| Deposited on: | 04 Aug 2011 11:51 |
| Last Modified: | 23 Feb 2017 17:41 |
