Power estimation and power optimization policies for processor-based systems

Abstract

This PhD Thesis proposes new and effective approaches to reduce and estímate the power
consumption in processor-based architectures. This work targets embedded systems, inorder
and out-of-order processors, cache hierarchies and MPSoCs. Our approaches are designad
to reduce or estimate the power consumption while keeping the performance constraints
of the application and allowing the porting to other processor architectures without a
hard effort by the designen
In this context, a first work was the design of a cache power estimation tool (called IN^
CAPE), which works in parallel with the processor simulator. The power estimation utihty
bases its results on an analytical power model, which has been fed with the expHcit calculation
of the statistical switching activity.
After that, reducing the power consumption in the register file of the processor architecture
was the goal of the research. Given that the register file is one of the most power-hungry
devices, firstly an efficient hardware mechanism to tum the unused registers of the register
file into a low power state has been described. A DVS technique is used to keep the Information
stored in the registers while reducing the power consumption to a mínimum. This
hardware technique has been compared to an approach based on a power-aware compiler,
which modifies the register assignment to improve the results obtained with the banking of
the register file, as well as to reduce the number of required ports.
Out-of-order architectures have also been addressed, with a higher degree of complexity.
For these systems, compiler and hardware approaches have also been proposed to efficiently
reduce the power consumption of the register file.
Finally, MPSoCs are also the new paradigm of high-performance microprocessor design,
where the power dissipation becomes an even more dramatic problem. These architectures
present complex design issues where the power-performance trade-off has to be carefully
analyzed in order to bring efficient designs. The work presented in this Ph. D. aims at
overcoming the limitation of theoretical and highly abstract models, unable to target the This PhD Thesis proposes new and effective approaches to reduce and estímate the power
consumption in processor-based architectures. This work targets embedded systems, inorder
and out-of-order processors, cache hierarchies and MPSoCs. Our approaches are designad
to reduce or estimate the power consumption while keeping the performance constraints
of the application and allowing the porting to other processor architectures without a
hard effort by the designen
In this context, a first work was the design of a cache power estimation tool (called IN^
CAPE), which works in parallel with the processor simulator. The power estimation utihty
bases its results on an analytical power model, which has been fed with the expHcit calculation
of the statistical switching activity.
After that, reducing the power consumption in the register file of the processor architecture
was the goal of the research. Given that the register file is one of the most power-hungry
devices, firstly an efficient hardware mechanism to tum the unused registers of the register
file into a low power state has been described. A DVS technique is used to keep the Information
stored in the registers while reducing the power consumption to a mínimum. This
hardware technique has been compared to an approach based on a power-aware compiler,
which modifies the register assignment to improve the results obtained with the banking of
the register file, as well as to reduce the number of required ports.
Out-of-order architectures have also been addressed, with a higher degree of complexity.
For these systems, compiler and hardware approaches have also been proposed to efficiently
reduce the power consumption of the register file.
Finally, MPSoCs are also the new paradigm of high-performance microprocessor design,
where the power dissipation becomes an even more dramatic problem. These architectures
present complex design issues where the power-performance trade-off has to be carefully
analyzed in order to bring efficient designs. The work presented in this Ph. D. aims at
overcoming the limitation of theoretical and highly abstract models, unable to target the desired functional simulation and power estimation. This work also presents interesting
results in terms of dynamic power management, voltage/frequency scaling and design space
exploration in MPSoCs.