eprintid: 21537 rev_number: 24 eprint_status: archive userid: 2544 dir: disk0/00/02/15/37 datestamp: 2013-11-11 07:38:50 lastmod: 2015-07-31 07:55:50 status_changed: 2013-11-11 07:38:50 type: thesis metadata_visibility: show item_issues_count: 0 creators_name: Gómez-Lobo García, Daniel contributors_name: Pescador del Oso, Fernando title: Methodologies for implement video decoders over multiprocessor platforms ispublished: unpub subjects: telecomunicaciones subjects: informatica abstract: The latest video coding standards developed, like HEVC (High Efficiency Video Coding, approved in January 2013), require for their implementation the use of devices able to support a high computational load. Considering that currently it is not enough the usage of one unique Digital Signal Processor (DSP), multicore devices have appeared recently in the market. However, due to its novelty, the working methodology that allows produce solutions for these configurations is in a very initial state, since currently the most part of the work needs to be performed manually. In consequence, the objective set consists on finding methodologies that ease this process. The study has been focused on extend a methodology, under development, for the generation of solutions for PCs and embedded systems. During this study, the standards RVC (Reconfigurable Video Coding) and HEVC have been employed, as well as DSPs of the Texas Instruments company. In its development, it has been tried to address all the factors that influence both the development and deployment of these new implementations of video decoders, ranging from tools up to aspects of the partitioning of algorithms, without this can cause a drop in application performance. The results of this study are the description of the employed methodology, the characterization of the software migration process and performance measurements for the HEVC standard in an RVC-based implementation. RESUMEN Los estándares de codificación de vídeo desarrollados más recientemente, como HEVC (High Efficiency Video Coding, aprobado en enero de 2013), requieren para su implementación el uso de dispositivos capaces de soportar una elevada carga computacional. Teniendo en cuenta que actualmente no es suficiente con utilizar un único Procesador Digital de Señal (DSP), han aparecido recientemente dispositivos multinúcleo en el mercado. Sin embargo, debido a su novedad, la metodología de trabajo que permite elaborar soluciones para tales configuraciones se encuentra en un estado muy inicial, ya que actualmente la mayor parte del trabajo debe realizarse manualmente. En consecuencia, el objetivo marcado consiste en encontrar metodologías que faciliten este proceso. El estudio se ha centrado en extender una metodología, en desarrollo, para la generación de soluciones para PC y sistemas empotrados. Durante dicho estudio se han empleado los estándares RVC (Reconfigurable Video Coding) y HEVC, así como DSPs de la compañía Texas Instruments. En su desarrollo se ha tratado de atender a todos los factores que influyen tanto en el desarrollo como en la puesta en marcha de estas nuevas implementaciones de descodificadores de vídeo; abarcando desde las herramientas a utilizar hasta aspectos del particionado de los algoritmos, sin que por ello se produzca una reducción en el rendimiento de las aplicaciones. Los resultados de este estudio son una descripción de la metodología empleada, la caracterización del proceso de migración de software, y medidas de rendimiento para el estándar HEVC en una implementación basada en RVC. date: 2013-07-18 date_type: published full_text_status: restricted pages: 135 institution: E_Telecomunicacion department: Sistemas_Electronicos thesis_type: masters referencetext: [1] S. S. Bhattacharyya, et al., “OpenDF - A Dataflow Toolset for Reconfigurable Hardware and Multicore Systems”. ACM SIGARCH Computer Architecture News, Volume 36 Issue 5, December 2008. [2] F. Pescador, “Contribución a las metodologías de optimización del tiempo de ejecución de algoritmos de descodificación de vídeo sobre DSPs”, Doctoral dissertation, Sistemas Electrónicos y de Control (SEC) department, E.U.I.T. de Telecomunicación, Technical University of Madrid, Spain, July 2011. [3] M. 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Pescador, et al, “Complexity Analysis of an HEVC decoder based on a Digital Signal Processor”, IEEE Transactions on Consumer Electronics (ICCE), Vol. 59 No. 2, pp. 391-399, May 2013. [52] F. Pescador, et al, “A DSP HEVC decoder implementation based on OpenHEVC”, IEEE Transactions on Consumer Electronics (ICCE), Paper sent to ICCE 2014. [53] ESTIMedia 2013 web site: http://www.estimedia.org/ [54] Crypto Tools Library (CTL) web site: http://www.hooklee.com/default.asp?t=CTL [55] Reconfigurable Media Coding article: http://ride.chiariglione.org/RMC.php [56] Oracle web site: www.oracle.com [57] Discussion in forum about how increase the Java heap: http://stackoverflow.com/questions/8600972/increasing-heap-space-in-eclipsejava-lang-outofmemoryerror rights: by-nc-nd master_title: Ingeniería de Sistemas y Servicios para la Sociedad de la Información citation: Gómez-Lobo García, Daniel (2013). Methodologies for implement video decoders over multiprocessor platforms. Thesis (Master thesis), E.U.I.T. Telecomunicación (UPM) . document_url: https://oa.upm.es/21537/1/TESIS_MASTER_DANIEL_GOMEZ_LOBO_GARCIA.pdf document_url: https://oa.upm.es/21537/2/TESIS_MASTER_DANIEL_GOMEZ_LOBO_GARCIA_ANEXOS.zip