?url_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Adc&rft.title=Versi%C3%B3n+2.0+de+un+modelo+en+VHDL+del+procesador+Mc68000&rft.creator=Yurkiv%2C+Serhiy&rft.contributor=Hermida+de+la+Rica%2C+Mariano&rft.subject=Computer+Science&rft.description=Este%0D%0Aproyecto%0D%0Aes+la+segunda+%0D%0Aversi%C3%B3n%0D%0Ade+un+trabajo+de+fin+de+grado+y+%0D%0Adescribe+las+%0D%0Afuncionalidades++a%C3%B1adidas+%0D%0Aal++proyecto+%0D%0Aya++comenzado.++El++proyecto++es++un++modelo++del+%0D%0Aprocesador+MC68000+en+el+lenguaje+de+descripci%C3%B3n+de+hardware+VHDL.%0D%0AEn+la+primera+%0D%0Aversi%C3%B3n%0D%0Adel++modelo++se++implement%C3%B3++la++arquitectura++simplificada++del++hardware++base++que+%0D%0Ahace++posible++la++simulaci%C3%B3n++del++procesador++adem%C3%A1s++de++una++parte++de++su++juego++de+%0D%0Ainstrucciones%0D%0A(ISA%2C++del++in%0D%0Agl%C3%A9s+%0D%0Ainstrucci%C3%B3n%0D%0Aset++architecture).++Los++subsistemas++han++sido+%0D%0Asimplificados+%0D%0Arespecto%0D%0Aa++la+%0D%0Aversi%C3%B3n%0D%0Areal++del++procesador.++Los++subsistemas++que++se++han+%0D%0Aimplementado+han+sido+%0D%0Ala+unidad+de+control%2C+la+ALU%2C+el+banco+de+registros%2C+el+contador+%0D%0Ade++programa%2C++el++registro%0D%0Ade++estado%2C++as%C3%AD++como++una++memoria++externa++sencilla++y++otros+%0D%0Am%C3%B3dulos++auxiliares++que++sirven++para++simular++el++comportamiento++de++las++se%C3%B1ales++internas+%0D%0Adel+procesador+con+el+programa+ModelSim.+%0D%0AEn+este+proyecto+se+ha+centrado+en+ampliar+%0D%0Ael+juego+de+%0D%0Ainstrucciones%0D%0Ay+modificar+la+arquitectura+para+as%C3%AD+acercar+m%C3%A1s+el+modelo+a+la+%0D%0Aversi%C3%B3n%0D%0Areal++del++procesador.++En++el++tiempo++que++dura++este++trabajo++de++fin++de++grado++no++da+%0D%0Atiempo+a+terminar+todo+el+juego+de+instrucciones+por+lo+tanto+habr%C3%A1+trabajo+para+terminar+%0D%0Ael+simulador.---ABSTRACT---This++project++is++the++second+%0D%0Aversion%0D%0Aof++a++final++degree++project++and++describes++the+%0D%0Afunctionalities++added++to++the++project++already++started.++The++project++is++a++model++of++the+%0D%0AMC68000+processor+in+the+VHDL+hardware+description+language.+In+the+first+%0D%0Aversion%0D%0Aof+%0D%0Athe++model%2C++the++simplified++architecture++of++the++base++hardware++was++implemented%2C++which+%0D%0Amakes++it++possible++to++simulate++the++processor++as++well++as++a++part++of++its+%0D%0Ainstruction%0D%0Aset+%0D%0Aarchitecture%0D%0A(ISA).++The++subsystems++have++been++simplified++relative++to++the++real+%0D%0Aversion%0D%0Aof+%0D%0Athe+processor.+The+subsystems+that+have+been+implemented+have+been+the+control+unit%2C+%0D%0Athe+ALU%2C+the+register+bank%2C+the+program+counter%2C+the+status+register%2C+as+well+as+a+simple+%0D%0Aexternal+memory+and+other+auxiliary+modules+that+%0D%0Ahelps+%0D%0Ato+simulate+the+behavior+of+the+%0D%0Asignals+of+the+processor+with+the+ModelSim+program.++In+this+project+he+has+focused+on+%0D%0Aexpanding++the++set++of++instructions++and++modifying++the++architecture++to++bring++the++model+%0D%0Acloser+to+the+real+%0D%0Aversi%C3%B3n%0D%0Aof+the+processor.+In+the+time+that+this+end-of-degree+work+lasts%2C+%0D%0Athere+is+no+time+to+finish+the+whole+set+of+instructions%2C+so+there+will+be+work+to+finish+the+%0D%0Asimulator.&rft.publisher=E.T.S.+de+Ingenieros+Inform%C3%83%C2%A1ticos+(UPM)&rft.rights=http%3A%2F%2Fcreativecommons.org%2Flicenses%2Fby-nc-nd%2F3.0%2Fes%2F&rft.date=2018-07&rft.type=info%3Aeu-repo%2Fsemantics%2FbachelorThesis&rft.type=Final+Project&rft.type=NonPeerReviewed&rft.format=application%2Fpdf&rft.language=spa&rft.rights=info%3Aeu-repo%2Fsemantics%2FopenAccess&rft.identifier=http%3A%2F%2Foa.upm.es%2F52825%2F