@unpublished{upm63440,
           month = {June},
            note = {Unpublished},
            year = {2019},
           title = {Entorno de test para la tarjeta de control del equipo de medici{\'o}n de distancias de Indra Sistemas},
         address = {Madrid},
          author = {Cano Moya, Alejandro},
        abstract = {En este documento se propone el dise{\~n}o de un entorno de test para una tarjeta de control o "control board", que se compondr{\'a} de una placa de test y del c{\'o}digo VHDL que se sintetizar{\'a} para ser volcado en la FPGA de la control board. Dado que en una multinacional el tiempo es dinero, cualquier mejora de producto que le permita detectar fallos superficiales autom{\'a}ticamente hace que se ahorre todo el tiempo y recursos que requerir{\'i}a la exploraci{\'o}n directa a las partes concretas del producto. Por ello, el planteamiento de un dise{\~n}o de una placa de test que autom{\'a}ticamente detecte fallos de los componentes m{\'a}s importantes de una control board supondr{\'i}a un enorme ahorro. Como la placa de testeo para la control board ha de ser lo menos costosa posible, se aprovechar{\'a}n todas las funciones posibles de la control board, por lo que el planteamiento inicial de la placa de test ser{\'a} la de una placa que, re-direccionando las distintas entradas y salidas de la control board le permita una autocomprobaci{\'o}n de sus distintas partes. Este trabajo de fin de grado concluir{\'a} con el dise{\~n}o a nivel de diagrama de bloques de la placa de test, el desarrollo del c{\'o}digo VHDL completo que una vez sintetizado se volcar{\'a} a la FPGA que contiene la control board y la simulaci{\'o}n de la respuesta del producto final en una prueba real.
Abstract:
In this document, we are going to propose the design of a test environment for a control board, which will consist of a test board and the VHDL code that will be synthesized and programmed into the FPGA control board. Given the fact that in a multinational time is money, any product improvement that allows detecting surface failures automatically saves all the time and resources that a deeper exploration of the specific parts of the product would require. Therefore, the approach of designing a test board that automatically detects failures of the most important components of a control board would be a huge saving. As the test board for the control board has to be as inexpensive as possible, all the possible functions of the control board will be used, so the initial approach of the test board will be that, redirecting the different inputs and outputs of the control board, allow a self-test of its different parts. This end-of-degree project will conclude with the design of the block diagram of the test board, the complete VHDL code that will be downloaded after synthesis to the FPGA contained in the control board and the simulation of the response of the final product in a real test.},
        keywords = {Placa de test; Control board},
             url = {https://oa.upm.es/63440/}
}