Texto completo
![[thumbnail of 10267050.pdf]](https://oa.upm.es/style/images/fileicons/application_pdf.png) |
PDF (Portable Document Format)
- Acceso permitido solamente al administrador del Archivo Digital UPM
- Se necesita un visor de ficheros PDF, como GSview, Xpdf o Adobe Acrobat Reader
Descargar (604kB) |
Applying the time-domain paradigm to interface multilevel phase change memory
Cita
Gracia Herranz, Amadeo de 
ORCID: https://orcid.org/0000-0003-0524-1746 and López Vallejo, Marisa ORCID: https://orcid.org/0000-0002-3833-524X
(2024).
Applying the time-domain paradigm to interface multilevel phase change memory.
En: "IEEE 24th International Conference on Nanotechnology (NANO)", 08/07/2024-11/07/2024, Gijón, España. p. 4.
https://doi.org/10.1109/NANO61778.2024.10628864.
ORCID: https://orcid.org/0000-0003-0524-1746 and López Vallejo, Marisa ORCID: https://orcid.org/0000-0002-3833-524X
(2024).
Applying the time-domain paradigm to interface multilevel phase change memory.
En: "IEEE 24th International Conference on Nanotechnology (NANO)", 08/07/2024-11/07/2024, Gijón, España. p. 4.
https://doi.org/10.1109/NANO61778.2024.10628864.
Descripción
| Título: | Applying the time-domain paradigm to interface multilevel phase change memory |
|---|---|
| Autor/es: |
|
| Tipo de Documento: | Ponencia en Congreso o Jornada (Artículo) |
| Título del Evento: | IEEE 24th International Conference on Nanotechnology (NANO) |
| Fechas del Evento: | 08/07/2024-11/07/2024 |
| Lugar del Evento: | Gijón, España |
| Título del Libro: | IEEE 24th International Conference on Nanotechnology (NANO) |
| Título de Revista/Publicación: | Proceedings of the IEEE Conference on Nanotechnology |
| Fecha: | 1 Enero 2024 |
| ISSN: | 19449380 |
| Materias: | |
| Palabras Clave Informales: | Phase change materials; resistance; power demand; nonvolatile memory; scalability; voltage; writing |
| Escuela: | E.T.S.I. Telecomunicación (UPM) |
| Departamento: | Ingeniería Electrónica |
| Licencias Creative Commons: | Ninguna |
Resumen
Phase Change Memory (PCM) is a prominent non-volatile memory technology that offers high-density, multilevel solutions. However, the circuitry required to read and write such devices has not been fully solved due to the highly non-linear behaviour of these devices and the complex voltage and current ranges required for reliable operation. Most of the proposed interfaces require very large area and power consumption and are accompanied by an odd form factor. This study explores time-domain interfaces as a potential solution for driving PCM cells by linking the physical attributes of the devices to a time variable. Here, we present a proof of concept for the implementation of time-domain interface architectures adapted to this type of memory.
Más información
| ID de Registro: | 87386 |
|---|---|
| Identificador DC: | https://oa.upm.es/87386/ |
| Identificador OAI: | oai:oa.upm.es:87386 |
| URL Portal Científico: | https://portalcientifico.upm.es/es/ipublic/item/10267050 |
| Identificador DOI: | 10.1109/NANO61778.2024.10628864 |
| URL Oficial: | https://ieeexplore.ieee.org/document/10628864 |
| Depositado por: | iMarina Portal Científico |
| Depositado el: | 30 Ene 2025 12:15 |
| Ultima Modificación: | 30 Ene 2025 12:15 |
Acciones
- Estadísticas
- Exportar cita
- Editar (sólo personal del Archivo)
