A Hardware-Efficient 1200-point FFT Architecture that Combines the Prime Factor and Cooley-Tukey Algorithms

Resumen

In this paper, we present a hardware-efficient 1200-point single-path delay feedback (SDF) fast Fourier transform (FFT) architecture. Contrary to previous FFT architectures for non-power-of-two (NP2) sizes, which usually require a large number of hardware resources, the proposed approach reduces significantly the rotators that are required in the architecture. This is achieved by combining the prime-factor and Cooley-Tukey algorithms. As a result, the proposed architecture has only one non-trivial rotator in between stages of the architecture.

The effectiveness of this optimization is demonstrated through experimental results, where the proposed approach achieves a significant improvement with respect to previous 1200-point FFTs in terms of hardware resources. Furthermore, the number of resources used in the proposed FFT and in previous optimized 1024-point FFTs is comparable. This fact is highly relevant since NP2 FFTs have traditionally been much less efficient than power-of-two (P2) FFTs. Thus, with this paper we break this old paradigm, making it possible to achieve with NP2 sizes similar efficiency as with P2 ones.