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ORCID: https://orcid.org/0000-0002-3847-8339, Garrido Gálvez, Mario
ORCID: https://orcid.org/0000-0001-5739-3544 and Karakonstantis, Georgios
(2023).
Energy-Efficient Short-Time Fourier Transform for Partial Window Overlapping.
En: "IEEE International Symposium on Circuits and Systems (ISCAS)", 21-25 May 2023, Monterey, CA, USA. ISBN 978-1-6654-5109-3.
https://doi.org/10.1109/ISCAS46773.2023.10181940.
| Título: | Energy-Efficient Short-Time Fourier Transform for Partial Window Overlapping |
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| Autor/es: |
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| Tipo de Documento: | Ponencia en Congreso o Jornada (Artículo) |
| Título del Evento: | IEEE International Symposium on Circuits and Systems (ISCAS) |
| Fechas del Evento: | 21-25 May 2023 |
| Lugar del Evento: | Monterey, CA, USA |
| Título del Libro: | Proceedings of the 2023 IEEE International Symposium on Circuits and Systems (ISCAS) |
| Fecha: | Mayo 2023 |
| ISBN: | 978-1-6654-5109-3 |
| Materias: | |
| Palabras Clave Informales: | Short-time Fourier transform, Hanning, frequency decomposition |
| Escuela: | E.T.S.I. Telecomunicación (UPM) |
| Departamento: | Ingeniería Electrónica |
| Grupo Investigación UPM: | Laboratorio de Sistemas Integrados LSI |
| Licencias Creative Commons: | Reconocimiento - Sin obra derivada - No comercial |
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This paper presents an energy-efficient short-time Fourier transform (STFT) architecture. The proposed architecture is called frequency decomposition STFT (FD-STFT) and it achieves significant computational complexity reduction by effectively re-utilizing previously computed spectrums between overlapped sampling windows. Such an algorithmic modification not only reduces the required hardware units, but also achieves low accumulative error compared to conventional approaches. In addition, the quality of the resulting spectrogram is improved by integrating an efficient hanning windowing technique that replaces the multiplication in the time domain, with a low-cost filtering in the frequency domain. For an $N$-point window with $R$ overlapping samples, the proposed architecture requires 3N -2N/R memory cells, (2N/R)(log(R)+1) multipliers and (2N/R)(log(R)+1) adders, while achieving up-to 40.86% and 65.56% area and power savings respectively, for hop size R=32, compared to recent approaches.
| ID de Registro: | 88002 |
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| Identificador DC: | https://oa.upm.es/88002/ |
| Identificador OAI: | oai:oa.upm.es:88002 |
| Identificador DOI: | 10.1109/ISCAS46773.2023.10181940 |
| URL Oficial: | https://ieeexplore.ieee.org/document/10181940 |
| Depositado por: | Dr. Mario Garrido Gálvez |
| Depositado el: | 25 Feb 2025 06:47 |
| Ultima Modificación: | 25 Feb 2025 06:47 |
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