Power Measurement Methodology for FPGA Devices

Jevtic, Ruzica and Carreras Vaquer, Carlos (2011). Power Measurement Methodology for FPGA Devices. "IEEE Transactions on Instrumentation and Measurement", v. 60 (n. 1); pp. 237-247. ISSN 0018-9456.


Title: Power Measurement Methodology for FPGA Devices
  • Jevtic, Ruzica
  • Carreras Vaquer, Carlos
Item Type: Article
Título de Revista/Publicación: IEEE Transactions on Instrumentation and Measurement
Date: 2011
Volume: 60
Faculty: E.T.S.I. Telecomunicación (UPM)
Department: Ingeniería Electrónica
Creative Commons Licenses: Recognition - No derivative works - Non commercial

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The efficiency of power optimization tools depends on information on design power provided by the power estimation models. Power models targeting different power groups can enable fast identification of the most power consuming parts of design and their properties. The accuracy of these estimation models is highly dependent on the accuracy of the method used for their characterization. The highest precision is achieved by using physical onboard measurements. In this paper, we present a measurement methodology that is primarily aimed at calibrating and validating high-level dynamic power estimation models. The measurements have been carefully designed to enable the separation of the interconnect power from the logic power and the power of the clock circuitry, so that each of these power groups can be used for the corresponding model validation. The standard measurement uncertainty is lower than 2% of the measured value even with a very small number of repeated measurements. Additionally, the accuracy of a commercial low-level power estimation tool has been also assessed for comparison purposes. The results indicate that the tool is not suitable for power estimation of data path-oriented designs.

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Item ID: 11621
DC Identifier: http://oa.upm.es/11621/
OAI Identifier: oai:oa.upm.es:11621
Deposited by: Memoria Investigacion
Deposited on: 10 Jul 2012 11:01
Last Modified: 20 Apr 2016 19:38
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