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Low-resource synchronous coincidence processor for positron emission tomography
Cita
Sportelli, Giancarlo, Belcari, Nicola, Guerra Gutiérrez, Pedro and Santos Lleo, Andres de 
ORCID: https://orcid.org/0000-0001-7423-9135
(2011).
Low-resource synchronous coincidence processor for positron emission tomography.
"Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment", v. 648
(n. Supple);
pp..
ISSN 0168-9002.
https://doi.org/10.1016/j.nima.2010.11.170.
ORCID: https://orcid.org/0000-0001-7423-9135
(2011).
Low-resource synchronous coincidence processor for positron emission tomography.
"Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment", v. 648
(n. Supple);
pp..
ISSN 0168-9002.
https://doi.org/10.1016/j.nima.2010.11.170.
Descripción
| Título: | Low-resource synchronous coincidence processor for positron emission tomography |
|---|---|
| Autor/es: |
|
| Tipo de Documento: | Artículo |
| Título de Revista/Publicación: | Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment |
| Fecha: | Agosto 2011 |
| ISSN: | 0168-9002 |
| Volumen: | 648 |
| Número: | Supple |
| Materias: | |
| ODS: | |
| Palabras Clave Informales: | Coincidence detection; Positronemissiontomography; FPGA; Spartan-3E; Spartan-6; 6 ns |
| Escuela: | E.T.S.I. Telecomunicación (UPM) |
| Departamento: | Ingeniería Electrónica |
| Licencias Creative Commons: | Reconocimiento - Sin obra derivada - No comercial |
Resumen
We developed a new FPGA-based method for coincidence detection in positronemissiontomography. The method requires low device resources and no specific peripherals in order to resolve coincident digital pulses within a time window of a few nanoseconds. This method has been validated with a low-end Xilinx Spartan-3E and provided coincidence resolutions lower than 6 ns. This resolution depends directly on the signal propagation properties of the target device and the maximum available clock frequency, therefore it is expected to improve considerably on higher-end FPGAs.
Más información
| ID de Registro: | 12116 |
|---|---|
| Identificador DC: | https://oa.upm.es/12116/ |
| Identificador OAI: | oai:oa.upm.es:12116 |
| URL Portal Científico: | https://portalcientifico.upm.es/es/ipublic/item/5486230 |
| Identificador DOI: | 10.1016/j.nima.2010.11.170 |
| URL Oficial: | http://www.sciencedirect.com/science/article/pii/S... |
| Depositado por: | Memoria Investigacion |
| Depositado el: | 11 Sep 2012 11:48 |
| Ultima Modificación: | 12 Nov 2025 00:00 |
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