Customizing floating-point units for FPGAs: Area-performance-standard trade-offs

López Vallejo, Marisa and Echeverría Aramendi, Pedro (2011). Customizing floating-point units for FPGAs: Area-performance-standard trade-offs. "Microprocessors And Microsystems", v. 35 (n. 6); pp. 535-546. ISSN 0141-9331. https://doi.org/10.1016/j.micpro.2011.04.004.

Description

Title: Customizing floating-point units for FPGAs: Area-performance-standard trade-offs
Author/s:
  • López Vallejo, Marisa
  • Echeverría Aramendi, Pedro
Item Type: Article
Título de Revista/Publicación: Microprocessors And Microsystems
Date: August 2011
ISSN: 0141-9331
Volume: 35
Subjects:
Faculty: E.T.S.I. Telecomunicación (UPM)
Department: Ingeniería Electrónica
Creative Commons Licenses: Recognition - No derivative works - Non commercial

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Abstract

The high integration density of current nanometer technologies allows the implementation of complex floating-point applications in a single FPGA. In this work the intrinsic complexity of floating-point operators is addressed targeting configurable devices and making design decisions providing the most suitable performance-standard compliance trade-offs. A set of floating-point libraries composed of adder/subtracter, multiplier, divisor, square root, exponential, logarithm and power function are presented. Each library has been designed taking into account special characteristics of current FPGAs, and with this purpose we have adapted the IEEE floating-point standard (software-oriented) to a custom FPGA-oriented format. Extended experimental results validate the design decisions made and prove the usefulness of reducing the format complexity

More information

Item ID: 12150
DC Identifier: http://oa.upm.es/12150/
OAI Identifier: oai:oa.upm.es:12150
DOI: 10.1016/j.micpro.2011.04.004
Deposited by: Memoria Investigacion
Deposited on: 10 Sep 2012 08:08
Last Modified: 21 Apr 2016 11:20
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