A Novel Scalable Deblocking-Filter Architecture for H.264/AVC and SVC Video Codecs

Cervero, Teresa and Otero Marnotes, Andres and López, S. and Torre Arnanz, Eduardo de la and Gallicó, G. and Sarmiento, Roberto and Riesgo Alcaide, Teresa (2011). A Novel Scalable Deblocking-Filter Architecture for H.264/AVC and SVC Video Codecs. In: "2011 IEEE International Conference on Multimedia and Expo (ICME)", 11/07/2011 - 15/07/2011, Barcelona, España. ISBN 978-1-61284-348-3. pp. 1-6.

Description

Title: A Novel Scalable Deblocking-Filter Architecture for H.264/AVC and SVC Video Codecs
Author/s:
  • Cervero, Teresa
  • Otero Marnotes, Andres
  • López, S.
  • Torre Arnanz, Eduardo de la
  • Gallicó, G.
  • Sarmiento, Roberto
  • Riesgo Alcaide, Teresa
Item Type: Presentation at Congress or Conference (Article)
Event Title: 2011 IEEE International Conference on Multimedia and Expo (ICME)
Event Dates: 11/07/2011 - 15/07/2011
Event Location: Barcelona, España
Title of Book: Proceedings of 2011 IEEE International Conference on Multimedia and Expo (ICME)
Date: September 2011
ISBN: 978-1-61284-348-3
Subjects:
Faculty: Centro de Electrónica Industrial (CEI) (UPM)
Department: Automática, Ingeniería Electrónica e Informática Industrial [hasta 2014]
Creative Commons Licenses: Recognition - No derivative works - Non commercial

Full text

[img]
Preview
PDF - Requires a PDF viewer, such as GSview, Xpdf or Adobe Acrobat Reader
Download (779kB) | Preview

Abstract

A highly parallel and scalable Deblocking Filter (DF) hardware architecture for H.264/AVC and SVC video codecs is presented in this paper. The proposed architecture mainly consists on a coarse grain systolic array obtained by replicating a unique and homogeneous Functional Unit (FU), in which a whole Deblocking-Filter unit is implemented. The proposal is also based on a novel macroblock-level parallelization strategy of the filtering algorithm which improves the final performance by exploiting specific data dependences. This way communication overhead is reduced and a more intensive parallelism in comparison with the existing state-of-the-art solutions is obtained. Furthermore, the architecture is completely flexible, since the level of parallelism can be changed, according to the application requirements. The design has been implemented in a Virtex-5 FPGA, and it allows filtering 4CIF (704 × 576 pixels @30 fps) video sequences in real-time at frequencies lower than 10.16 Mhz.

More information

Item ID: 12900
DC Identifier: http://oa.upm.es/12900/
OAI Identifier: oai:oa.upm.es:12900
Official URL: http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=6012075
Deposited by: Memoria Investigacion
Deposited on: 08 Nov 2012 11:39
Last Modified: 21 Apr 2016 12:13
  • Logo InvestigaM (UPM)
  • Logo GEOUP4
  • Logo Open Access
  • Open Access
  • Logo Sherpa/Romeo
    Check whether the anglo-saxon journal in which you have published an article allows you to also publish it under open access.
  • Logo Dulcinea
    Check whether the spanish journal in which you have published an article allows you to also publish it under open access.
  • Logo de Recolecta
  • Logo del Observatorio I+D+i UPM
  • Logo de OpenCourseWare UPM