Cost and energy efficient reconfigurable embedded platform using Spartan-6 FPGAs

Otero Marnotes, Andres and Llinás, M. and Lombardo, Miguel and Portilla Berrueco, Jorge and Torre Arnanz, Eduardo de la and Riesgo Alcaide, Teresa (2011). Cost and energy efficient reconfigurable embedded platform using Spartan-6 FPGAs. In: "VLSI Circuits and Systems V", 18/04/2011 - 20/04/2011, Praga, República Checa. pp. 1-13.

Description

Title: Cost and energy efficient reconfigurable embedded platform using Spartan-6 FPGAs
Author/s:
  • Otero Marnotes, Andres
  • Llinás, M.
  • Lombardo, Miguel
  • Portilla Berrueco, Jorge
  • Torre Arnanz, Eduardo de la
  • Riesgo Alcaide, Teresa
Item Type: Presentation at Congress or Conference (Article)
Event Title: VLSI Circuits and Systems V
Event Dates: 18/04/2011 - 20/04/2011
Event Location: Praga, República Checa
Title of Book: Proceedings of SPIE VLSI Circuits and Systems V
Date: 2011
Volume: 8067
Subjects:
Faculty: Centro de Electrónica Industrial (CEI) (UPM)
Department: Automática, Ingeniería Electrónica e Informática Industrial [hasta 2014]
Creative Commons Licenses: Recognition - No derivative works - Non commercial

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Abstract

Modern FPGAs with run-time reconfiguration allow the implementation of complex systems offering both the flexibility of software-based solutions combined with the performance of hardware. This combination of characteristics, together with the development of new specific methodologies, make feasible to reach new points of the system design space, and make embedded systems built on these platforms acquire more and more importance. However, the practical exploitation of this technique in fields that traditionally have relied on resource restricted embedded systems, is mainly limited by strict power consumption requirements, the cost and the high dependence of DPR techniques with the specific features of the device technology underneath. In this work, we tackle the previously reported problems, designing a reconfigurable platform based on the low-cost and low-power consuming Spartan-6 FPGA family. The full process to develop the platform will be detailed in the paper from scratch. In addition, the implementation of the reconfiguration mechanism, including two profiles, is reported. The first profile is a low-area and low-speed reconfiguration engine based mainly on software functions running on the embedded processor, while the other one is a hardware version of the same engine, implemented in the FPGA logic. This reconfiguration hardware block has been originally designed to the Virtex-5 family, and its porting process will be also described in this work, facing the interoperability problem among different families.

More information

Item ID: 13034
DC Identifier: http://oa.upm.es/13034/
OAI Identifier: oai:oa.upm.es:13034
Deposited by: Memoria Investigacion
Deposited on: 05 Dec 2012 11:38
Last Modified: 21 Apr 2016 12:20
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