Cost and energy efficient reconfigurable embedded platform using Spartan-6 FPGAs

Otero Marnotes, Andres; Llinás, M.; Lombardo, Miguel; Portilla Berrueco, Jorge; Torre Arnanz, Eduardo de la y Riesgo Alcaide, Teresa (2011). Cost and energy efficient reconfigurable embedded platform using Spartan-6 FPGAs. En: "VLSI Circuits and Systems V", 18/04/2011 - 20/04/2011, Praga, República Checa. pp. 1-13.

Descripción

Título: Cost and energy efficient reconfigurable embedded platform using Spartan-6 FPGAs
Autor/es:
  • Otero Marnotes, Andres
  • Llinás, M.
  • Lombardo, Miguel
  • Portilla Berrueco, Jorge
  • Torre Arnanz, Eduardo de la
  • Riesgo Alcaide, Teresa
Tipo de Documento: Ponencia en Congreso o Jornada (Artículo)
Título del Evento: VLSI Circuits and Systems V
Fechas del Evento: 18/04/2011 - 20/04/2011
Lugar del Evento: Praga, República Checa
Título del Libro: Proceedings of SPIE VLSI Circuits and Systems V
Fecha: 2011
Volumen: 8067
Materias:
Escuela: Centro de Electrónica Industrial (CEI) (UPM)
Departamento: Automática, Ingeniería Electrónica e Informática Industrial [hasta 2014]
Licencias Creative Commons: Reconocimiento - Sin obra derivada - No comercial

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Resumen

Modern FPGAs with run-time reconfiguration allow the implementation of complex systems offering both the flexibility of software-based solutions combined with the performance of hardware. This combination of characteristics, together with the development of new specific methodologies, make feasible to reach new points of the system design space, and make embedded systems built on these platforms acquire more and more importance. However, the practical exploitation of this technique in fields that traditionally have relied on resource restricted embedded systems, is mainly limited by strict power consumption requirements, the cost and the high dependence of DPR techniques with the specific features of the device technology underneath. In this work, we tackle the previously reported problems, designing a reconfigurable platform based on the low-cost and low-power consuming Spartan-6 FPGA family. The full process to develop the platform will be detailed in the paper from scratch. In addition, the implementation of the reconfiguration mechanism, including two profiles, is reported. The first profile is a low-area and low-speed reconfiguration engine based mainly on software functions running on the embedded processor, while the other one is a hardware version of the same engine, implemented in the FPGA logic. This reconfiguration hardware block has been originally designed to the Virtex-5 family, and its porting process will be also described in this work, facing the interoperability problem among different families.

Más información

ID de Registro: 13034
Identificador DC: http://oa.upm.es/13034/
Identificador OAI: oai:oa.upm.es:13034
Depositado por: Memoria Investigacion
Depositado el: 05 Dic 2012 11:38
Ultima Modificación: 21 Abr 2016 12:20
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