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Evolvable 2D computing matrix model for intrinsic evolution in commercial FPGAs with native reconfiguration support
Cita
Salvador Perea, Rubén 
ORCID: https://orcid.org/0000-0002-0021-5808, Otero Marnotes, Andres, Mora, Javier, Torre Arnanz, Eduardo de la ORCID: https://orcid.org/0000-0001-5697-0573, Riesgo Alcaide, Teresa ORCID: https://orcid.org/0000-0003-0532-8681 and Sekanina, Lukás
(2011).
Evolvable 2D computing matrix model for intrinsic evolution in commercial FPGAs with native reconfiguration support.
En: "2011 NASA/ESA Conference on Adaptive Hardware and Systems (AHS)", 06/06/2011 - 09/06/2011, San Diego, CA, EEUU. ISBN 978-1-4577-0598-4. pp. 184-191.
ORCID: https://orcid.org/0000-0002-0021-5808, Otero Marnotes, Andres, Mora, Javier, Torre Arnanz, Eduardo de la ORCID: https://orcid.org/0000-0001-5697-0573, Riesgo Alcaide, Teresa ORCID: https://orcid.org/0000-0003-0532-8681 and Sekanina, Lukás
(2011).
Evolvable 2D computing matrix model for intrinsic evolution in commercial FPGAs with native reconfiguration support.
En: "2011 NASA/ESA Conference on Adaptive Hardware and Systems (AHS)", 06/06/2011 - 09/06/2011, San Diego, CA, EEUU. ISBN 978-1-4577-0598-4. pp. 184-191.
Descripción
| Título: | Evolvable 2D computing matrix model for intrinsic evolution in commercial FPGAs with native reconfiguration support |
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| Autor/es: |
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| Tipo de Documento: | Ponencia en Congreso o Jornada (Artículo) |
| Título del Evento: | 2011 NASA/ESA Conference on Adaptive Hardware and Systems (AHS) |
| Fechas del Evento: | 06/06/2011 - 09/06/2011 |
| Lugar del Evento: | San Diego, CA, EEUU |
| Título del Libro: | Proceedings of 2011 NASA/ESA Conference on Adaptive Hardware and Systems (AHS) |
| Fecha: | 2011 |
| ISBN: | 978-1-4577-0598-4 |
| Materias: | |
| ODS: | |
| Escuela: | E.U.I.T. Telecomunicación (UPM) [antigua denominación] |
| Departamento: | Sistemas Electrónicos y de Control [hasta 2014] |
| Licencias Creative Commons: | Reconocimiento - Sin obra derivada - No comercial |
Resumen
This paper addresses the modelling and validation of an evolvable hardware architecture which can be mapped on a 2D systolic structure implemented on commercial reconfigurable FPGAs. The adaptation capabilities of the architecture are exercised to validate its evolvability. The underlying proposal is the use of a library of reconfigurable components characterised by their partial bitstreams, which are used by the Evolutionary Algorithm to find a solution to a given task. Evolution of image noise filters is selected as the proof of concept application. Results show that computation speed of the resulting evolved circuit is higher than with the Virtual Reconfigurable Circuits approach, and this can be exploited on the evolution process by using dynamic reconfiguration
Más información
| ID de Registro: | 13323 |
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| Identificador DC: | https://oa.upm.es/13323/ |
| Identificador OAI: | oai:oa.upm.es:13323 |
| URL Oficial: | http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumb... |
| Depositado por: | Memoria Investigacion |
| Depositado el: | 28 Nov 2012 09:02 |
| Ultima Modificación: | 21 Abr 2016 12:38 |
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