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Run-time Scalable Architecture for Deblocking Filtering in H.264/AVC-SVC Video Codecs
Cita
Otero Marnotes, Andres, Torre Arnanz, Eduardo de la 
ORCID: https://orcid.org/0000-0001-5697-0573, Riesgo Alcaide, Teresa ORCID: https://orcid.org/0000-0003-0532-8681, Cervero, Teresa, López, S., Gallicó, G. and Sarmiento, Roberto
(2011).
Run-time Scalable Architecture for Deblocking Filtering in H.264/AVC-SVC Video Codecs.
En: "21st International Conference on Field Programmable Logic and Applications", 05/09/2011 - 07/09/2011, Creta, Grecia. ISBN 978-1-4577-1484-9. pp. 1-6.
ORCID: https://orcid.org/0000-0001-5697-0573, Riesgo Alcaide, Teresa ORCID: https://orcid.org/0000-0003-0532-8681, Cervero, Teresa, López, S., Gallicó, G. and Sarmiento, Roberto
(2011).
Run-time Scalable Architecture for Deblocking Filtering in H.264/AVC-SVC Video Codecs.
En: "21st International Conference on Field Programmable Logic and Applications", 05/09/2011 - 07/09/2011, Creta, Grecia. ISBN 978-1-4577-1484-9. pp. 1-6.
Descripción
| Título: | Run-time Scalable Architecture for Deblocking Filtering in H.264/AVC-SVC Video Codecs |
|---|---|
| Autor/es: |
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| Tipo de Documento: | Ponencia en Congreso o Jornada (Artículo) |
| Título del Evento: | 21st International Conference on Field Programmable Logic and Applications |
| Fechas del Evento: | 05/09/2011 - 07/09/2011 |
| Lugar del Evento: | Creta, Grecia |
| Título del Libro: | Proceedings of 21st International Conference on Field Programmable Logic and Applications |
| Fecha: | 2011 |
| ISBN: | 978-1-4577-1484-9 |
| Materias: | |
| ODS: | |
| Escuela: | E.T.S.I. Industriales (UPM) |
| Departamento: | Automática, Ingeniería Electrónica e Informática Industrial [hasta 2014] |
| Licencias Creative Commons: | Reconocimiento - Sin obra derivada - No comercial |
Resumen
Systems relying on fixed hardware components with a static level of parallelism can suffer from an underuse of logical resources, since they have to be designed for the worst-case scenario. This problem is especially important in video applications due to the emergence of new flexible standards, like Scalable Video Coding (SVC), which offer several levels of scalability. In this paper, Dynamic and Partial Reconfiguration (DPR) of modern FPGAs is used to achieve run-time variable parallelism, by using scalable architectures where the size can be adapted at run-time. Based on this proposal, a scalable Deblocking Filter core (DF), compliant with the H.264/AVC and SVC standards has been designed. This scalable DF allows run-time addition or removal of computational units working in parallel. Scalability is offered together with a scalable parallelization strategy at the macroblock (MB) level, such that when the size of the architecture changes, MB filtering order is modified accordingly
Más información
| ID de Registro: | 13355 |
|---|---|
| Identificador DC: | https://oa.upm.es/13355/ |
| Identificador OAI: | oai:oa.upm.es:13355 |
| URL Oficial: | http://ieeexplore.ieee.org/xpl/articleDetails.jsp?... |
| Depositado por: | Memoria Investigacion |
| Depositado el: | 24 Oct 2012 10:48 |
| Ultima Modificación: | 21 Abr 2016 12:40 |
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