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IDRA (IDeal Resource Allocation): Computing ideal speedups in parallel logic programming
Cita
Fernandez, M.J., Carro Liñares, Manuel 
ORCID: https://orcid.org/0000-0001-5199-3135 and Hermenegildo, Manuel V. ORCID: https://orcid.org/0000-0002-7583-323X
(1996).
IDRA (IDeal Resource Allocation): Computing ideal speedups in parallel logic programming.
En: "Second International Euro-Par Conference", August 26-29, 1996, Lyon, France. ISBN 9783540616276.
ORCID: https://orcid.org/0000-0001-5199-3135 and Hermenegildo, Manuel V. ORCID: https://orcid.org/0000-0002-7583-323X
(1996).
IDRA (IDeal Resource Allocation): Computing ideal speedups in parallel logic programming.
En: "Second International Euro-Par Conference", August 26-29, 1996, Lyon, France. ISBN 9783540616276.
Descripción
| Título: | IDRA (IDeal Resource Allocation): Computing ideal speedups in parallel logic programming |
|---|---|
| Autor/es: |
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| Tipo de Documento: | Ponencia en Congreso o Jornada (Artículo) |
| Título del Evento: | Second International Euro-Par Conference |
| Fechas del Evento: | August 26-29, 1996 |
| Lugar del Evento: | Lyon, France |
| Título del Libro: | Euro-Par'96 Parallel Processing |
| Fecha: | Agosto 1996 |
| ISBN: | 9783540616276 |
| Volumen: | 1124 |
| Materias: | |
| ODS: | |
| Palabras Clave Informales: | Parallel logic programming, Simulation, Parallelism, Concurrency,Performance evaluation, Programación lógica paralela, Simulación, Paralelismo, Concurrencia, Evaluación de resultados. |
| Escuela: | Facultad de Informática (UPM) [antigua denominación] |
| Departamento: | Inteligencia Artificial |
| Licencias Creative Commons: | Reconocimiento - Sin obra derivada - No comercial |
Resumen
We present a technique to estimate accurate speedups for parallel logic programs with relative independence from characteristics of a given implementation or underlying parallel hardware. The proposed technique is based on gathering accurate data describing one execution at run-time, which is fed to a simulator. Alternative schedulings are then simulated and estimates computed for the corresponding speedups. A tool implementing the aforementioned techniques is presented, and its predictions are compared to the performance of real systems, showing good correlation.
Más información
| ID de Registro: | 14419 |
|---|---|
| Identificador DC: | https://oa.upm.es/14419/ |
| Identificador OAI: | oai:oa.upm.es:14419 |
| URL Oficial: | http://link.springer.com/chapter/10.1007%2FBFb0024... |
| Depositado por: | Biblioteca Facultad de Informatica |
| Depositado el: | 05 Feb 2013 19:56 |
| Ultima Modificación: | 27 Feb 2023 12:23 |
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