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ORCID: https://orcid.org/0000-0002-7583-323X
(1987).
Relating goal scheduling, precedence, and memory management in and-parallel execution of logic programs.
En: "Fourth International Conference on Logis Programming", May 25-29, 1987, Melbourne, Victoria, Australia. ISBN 0262121255.
| Título: | Relating goal scheduling, precedence, and memory management in and-parallel execution of logic programs |
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| Autor/es: |
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| Tipo de Documento: | Ponencia en Congreso o Jornada (Artículo) |
| Título del Evento: | Fourth International Conference on Logis Programming |
| Fechas del Evento: | May 25-29, 1987 |
| Lugar del Evento: | Melbourne, Victoria, Australia |
| Título del Libro: | Logic programming, Proceedings of the Fourth International Conference |
| Fecha: | Mayo 1987 |
| ISBN: | 0262121255 |
| Materias: | |
| ODS: | |
| Palabras Clave Informales: | Logic programming, parallel processing, and-paralelism, Scheduling, Memory management, Coroutining, Prolog, Programación lógica, procesamiento paralelo, Programación, Gestión de la memoria. |
| Escuela: | Facultad de Informática (UPM) [antigua denominación] |
| Departamento: | Inteligencia Artificial |
| Licencias Creative Commons: | Reconocimiento - Sin obra derivada - No comercial |
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The interactions among three important issues involved in the implementation of logic programs in parallel (goal scheduling, precedence, and memory management) are discussed. A simplified, parallel memory management model and an efficient, load-balancing goal scheduling strategy are presented. It is shown how, for systems which support "don't know" non-determinism, special care has to be taken during goal scheduling if the space recovery characteristics of sequential systems are to be preserved. A solution based on selecting only "newer" goals for execution is described, and an algorithm is proposed for efficiently maintaining and determining precedence relationships and variable ages across parallel goals. It is argued that the proposed schemes and algorithms make it possible to extend the storage performance of sequential systems to parallel execution without the considerable overhead previously associated with it. The results are applicable to a wide class of parallel and coroutining systems, and they represent an efficient alternative to "all heap" or "spaghetti stack" allocation models.
| ID de Registro: | 14531 |
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| Identificador DC: | https://oa.upm.es/14531/ |
| Identificador OAI: | oai:oa.upm.es:14531 |
| Depositado por: | Biblioteca Facultad de Informatica |
| Depositado el: | 21 Feb 2013 08:14 |
| Ultima Modificación: | 27 Feb 2023 11:51 |
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