An Interleaved EPE-Immune PA-DPL Structure for Resisting Concentrated EM Side Channel Attacks on FPGA Implementation

He, Wei and Torre Arnanz, Eduardo de la and Riesgo Alcaide, Teresa (2012). An Interleaved EPE-Immune PA-DPL Structure for Resisting Concentrated EM Side Channel Attacks on FPGA Implementation. In: "Third International Workshop, COSADE 2012,", 03/05/2012 - 04/05/2012, Darmstadt, Alemania. ISBN 978-3-642-29911-7. pp. 39-53.

Description

Title: An Interleaved EPE-Immune PA-DPL Structure for Resisting Concentrated EM Side Channel Attacks on FPGA Implementation
Author/s:
  • He, Wei
  • Torre Arnanz, Eduardo de la
  • Riesgo Alcaide, Teresa
Item Type: Presentation at Congress or Conference (Article)
Event Title: Third International Workshop, COSADE 2012,
Event Dates: 03/05/2012 - 04/05/2012
Event Location: Darmstadt, Alemania
Title of Book: Constructive Side-Channel Analysis and Secure Design Third International Workshop, COSADE 2012, Darmstadt, Germany, May 3-4, 2012. Proceedings
Date: 2012
ISBN: 978-3-642-29911-7
Subjects:
Faculty: Centro de Electrónica Industrial (CEI) (UPM)
Department: Otro
Creative Commons Licenses: Recognition - No derivative works - Non commercial

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Abstract

Early propagation effect (EPE) is a critical problem in conventional dual-rail logic implementations against Side Channel Attacks (SCAs). Among previous EPE-resistant architectures, PA-DPL logic offers EPE-free capability at relatively low cost. However, its separate dual core structure is a weakness when facing concentrated EM attacks where a tiny EM probe can be precisely positioned closer to one of the two cores. In this paper, we present an PA-DPL dual-core interleaved structure to strengthen resistance against sophisticated EM attacks on Xilinx FPGA implementations. The main merit of the proposed structure is that every two routing in each signal pair are kept identical even the dual cores are interleaved together. By minimizing the distance between the complementary routings and instances of both cores, even the concentrated EM measurement cannot easily distinguish the minor EM field unbalance. In PA- DPL, EPE is avoided by compressing the evaluation phase to a small portion of the clock period, therefore, the speed is inevitably limited. Regarding this, we made an improvement to extend the duty cycle of evaluation phase to more than 40 percent, yielding a larger maximum working frequency. The detailed design flow is also presented. We validate the security improvement against EM attack by implementing a simplified AES co-processor in Virtex-5 FPGA.

More information

Item ID: 19201
DC Identifier: http://oa.upm.es/19201/
OAI Identifier: oai:oa.upm.es:19201
Deposited by: Memoria Investigacion
Deposited on: 16 Sep 2013 14:43
Last Modified: 21 Apr 2016 17:27
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