Synchronous Buck converter with Output Impedance Correction Circuit

Svikovic, Vladimir; Oliver Ramírez, Jesús Angel; Alou Cervera, Pedro; García Suárez, Oscar y Cobos Márquez, José Antonio (2012). Synchronous Buck converter with Output Impedance Correction Circuit. En: "Applied Power Electronics Conference and Exposition (APEC), 2012 Twenty-Seventh Annual IEEE", 05/02/2012 - 09/02/2012, Orlando (Florida, USA). ISBN 978-1-4577-1215-9. pp. 727-734.

Descripción

Título: Synchronous Buck converter with Output Impedance Correction Circuit
Autor/es:
  • Svikovic, Vladimir
  • Oliver Ramírez, Jesús Angel
  • Alou Cervera, Pedro
  • García Suárez, Oscar
  • Cobos Márquez, José Antonio
Tipo de Documento: Ponencia en Congreso o Jornada (Artículo)
Título del Evento: Applied Power Electronics Conference and Exposition (APEC), 2012 Twenty-Seventh Annual IEEE
Fechas del Evento: 05/02/2012 - 09/02/2012
Lugar del Evento: Orlando (Florida, USA)
Título del Libro: Applied Power Electronics Conference and Exposition (APEC), 2012 Twenty-Seventh Annual IEEE
Fecha: Febrero 2012
ISBN: 978-1-4577-1215-9
Materias:
Escuela: Centro de Electrónica Industrial (CEI) (UPM)
Departamento: Otro
Licencias Creative Commons: Reconocimiento - Sin obra derivada - No comercial

Texto completo

[img] PDF (Document Portable Format) - Acceso permitido solamente a usuarios en el campus de la UPM - Se necesita un visor de ficheros PDF, como GSview, Xpdf o Adobe Acrobat Reader
Descargar (3MB)

Resumen

This work is related to the improvement of the output impedance of the Buck converter by means of introducing an additional power path that virtually increases the output capacitance during transients. It is well known that in VRM applications, with wide load steps, voltage overshoots and undershoots may lead to undesired performance of the load. To solve this problem, high-bandwidth high-switching frequency power converters can be applied to reduce the transient time or a big output capacitor can be applied to reduce the output impedance. The first solution can degrade the efficiency by increasing switching losses of the MOSFETS, and the second solution is penalizing the cost and size of the output filter. The Output Impedance Correction Circuit (OICC), as presented here, is used to inject or extract a current n-1 times larger than the output capacitor current, thus virtually increasing n times the value of the output capacitance during the transients. This feature allows the usage of a low frequency Buck converter with smaller capacitor but satisfying the dynamic requirements.

Más información

ID de Registro: 20865
Identificador DC: http://oa.upm.es/20865/
Identificador OAI: oai:oa.upm.es:20865
URL Oficial: http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6165900
Depositado por: Memoria Investigacion
Depositado el: 12 Nov 2013 18:57
Ultima Modificación: 22 Sep 2014 11:21
  • Open Access
  • Open Access
  • Sherpa-Romeo
    Compruebe si la revista anglosajona en la que ha publicado un artículo permite también su publicación en abierto.
  • Dulcinea
    Compruebe si la revista española en la que ha publicado un artículo permite también su publicación en abierto.
  • Recolecta
  • e-ciencia
  • Observatorio I+D+i UPM
  • OpenCourseWare UPM