Implementation techniques for evolvable HW systems: virtual vs. dynamic reconfiguration

Salvador Perea, Rubén and Otero Marnotes, Andres and Torre Arnanz, Eduardo de la and Riesgo Alcaide, Teresa and Mora de Sambricio, Javier and Sekanina, Lukás (2012). Implementation techniques for evolvable HW systems: virtual vs. dynamic reconfiguration. In: "22nd International Conference on Field Programmable Logic and Applications (FPL2012)", 29/08/2012 - 31/08/2012, Oslo (Norway). ISBN 978-1-4673-2257-7. pp. 547-550.

Description

Title: Implementation techniques for evolvable HW systems: virtual vs. dynamic reconfiguration
Author/s:
  • Salvador Perea, Rubén
  • Otero Marnotes, Andres
  • Torre Arnanz, Eduardo de la
  • Riesgo Alcaide, Teresa
  • Mora de Sambricio, Javier
  • Sekanina, Lukás
Item Type: Presentation at Congress or Conference (Article)
Event Title: 22nd International Conference on Field Programmable Logic and Applications (FPL2012)
Event Dates: 29/08/2012 - 31/08/2012
Event Location: Oslo (Norway)
Title of Book: 22nd International Conference on Field Programmable Logic and Applications (FPL), 2012
Date: 2012
ISBN: 978-1-4673-2257-7
Subjects:
Freetext Keywords: field programmable gate arrays; filtering theory; image processing
Faculty: E.U.I.T. Telecomunicación (UPM)
Department: Sistemas Electrónicos y de Control [hasta 2014]
Creative Commons Licenses: Recognition - No derivative works - Non commercial

Full text

[img]
Preview
PDF - Requires a PDF viewer, such as GSview, Xpdf or Adobe Acrobat Reader
Download (7MB)

Abstract

Adaptive hardware requires some reconfiguration capabilities. FPGAs with native dynamic partial reconfiguration (DPR) support pose a dilemma for system designers: whether to use native DPR or to build a virtual reconfigurable circuit (VRC) on top of the FPGA which allows selecting alternative functions by a multiplexing scheme. This solution allows much faster reconfiguration, but with higher resource overhead. This paper discusses the advantages of both implementations for a 2D image processing matrix. Results show how higher operating frequency is obtained for the matrix using DPR. However, this is compensated in the VRC during evolution due to the comparatively negligible reconfiguration time. Regarding area, the DPR implementation consumes slightly more resources due to the reconfiguration engine, but adds further more capabilities to the system.

More information

Item ID: 20880
DC Identifier: http://oa.upm.es/20880/
OAI Identifier: oai:oa.upm.es:20880
Official URL: http://fpl2012.org/
Deposited by: Memoria Investigacion
Deposited on: 02 Apr 2014 18:04
Last Modified: 25 May 2015 14:33
  • Logo InvestigaM (UPM)
  • Logo GEOUP4
  • Logo Open Access
  • Open Access
  • Logo Sherpa/Romeo
    Check whether the anglo-saxon journal in which you have published an article allows you to also publish it under open access.
  • Logo Dulcinea
    Check whether the spanish journal in which you have published an article allows you to also publish it under open access.
  • Logo de Recolecta
  • Logo del Observatorio I+D+i UPM
  • Logo de OpenCourseWare UPM