Dreams: A tool for the design of dynamically reconfigurable embedded and modular systems

Otero Marnotes, Andres; Torre Arnanz, Eduardo de la y Riesgo Alcaide, Teresa (2012). Dreams: A tool for the design of dynamically reconfigurable embedded and modular systems. En: "Proceedings of International Conference on ReConFigurable Computing and FPGAs (ReConFig)", 05/12/2012 - 07/12/2012, Cancun (Mexico). pp. 1-8.

Descripción

Título: Dreams: A tool for the design of dynamically reconfigurable embedded and modular systems
Autor/es:
  • Otero Marnotes, Andres
  • Torre Arnanz, Eduardo de la
  • Riesgo Alcaide, Teresa
Tipo de Documento: Ponencia en Congreso o Jornada (Artículo)
Título del Evento: Proceedings of International Conference on ReConFigurable Computing and FPGAs (ReConFig)
Fechas del Evento: 05/12/2012 - 07/12/2012
Lugar del Evento: Cancun (Mexico)
Título del Libro: Reconfigurable Computing and FPGAs (ReConFig), 2012 International Conference on
Fecha: 2012
Materias:
Escuela: Centro de Electrónica Industrial (CEI) (UPM)
Departamento: Otro
Licencias Creative Commons: Reconocimiento - Sin obra derivada - No comercial

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Resumen

Dynamically Reconfigurable Systems are attracting a growing interest, mainly due to the emergence of novel applications based on this technology. However, commercial tools do not provide enough flexibility to design solutions, while keeping an acceptable design productivity. In this paper, a novel design flow is proposed, targeting dynamically reconfigurable systems. It is fully supported by a tool called Dreams, which is able to implement flexible systems, starting from a set of netlists corresponding to the modules, as well as a system description provided by the user. The tool automatically post-processes the nets, implementing a solution for the communications between reconfigurable regions, as well as the handling of routing conflicts, by means of a custom router. Since the design process of every module and the static system are independent, the proposed flow is compatible with system upgrade at run-time. In this paper, a use case corresponding to the design of a highly regular and parallel mesh-type architecture is described, in order to show the architectural flexibility offered by the tool.

Más información

ID de Registro: 20888
Identificador DC: http://oa.upm.es/20888/
Identificador OAI: oai:oa.upm.es:20888
URL Oficial: http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6416740
Depositado por: Memoria Investigacion
Depositado el: 19 Nov 2013 19:13
Ultima Modificación: 22 Sep 2014 11:21
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