Automatic Generation of Identical Routing Pairs for FPGA Implemented DPL Logic

He, Wei and Otero Marnotes, Andres and Torre Arnanz, Eduardo de la and Riesgo Alcaide, Teresa (2012). Automatic Generation of Identical Routing Pairs for FPGA Implemented DPL Logic. In: "Proceedings of International Conference on ReConFigurable Computing and FPGAs (ReConFig)", 05/12/2012 - 07/12/2012, Cancun (Mexico). ISBN 978-1-4673-2919-4. pp. 1-6.

Description

Title: Automatic Generation of Identical Routing Pairs for FPGA Implemented DPL Logic
Author/s:
  • He, Wei
  • Otero Marnotes, Andres
  • Torre Arnanz, Eduardo de la
  • Riesgo Alcaide, Teresa
Item Type: Presentation at Congress or Conference (Article)
Event Title: Proceedings of International Conference on ReConFigurable Computing and FPGAs (ReConFig)
Event Dates: 05/12/2012 - 07/12/2012
Event Location: Cancun (Mexico)
Title of Book: Reconfigurable Computing and FPGAs (ReConFig), 2012 International Conference on
Date: 2012
ISBN: 978-1-4673-2919-4
Subjects:
Faculty: Centro de Electrónica Industrial (CEI) (UPM)
Department: Otro
Creative Commons Licenses: Recognition - No derivative works - Non commercial

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Abstract

Side Channel Attacks (SCAs) typically gather unintentional (side channel) physical leakages from running crypto-devices to reveal confidential data. Dual-rail Precharge Logic (DPL) is one of the most efficient countermeasures against power or EM side channel threats. This logic relies on the implementation of complementary rails to counterbalance the data-dependent variations of the leakage from dynamic behavior of the original circuit. However, the lack of flexibility of commercial FPGA design tools makes it quite difficult to obtain completely balanced routings between complementary networks. In this paper, a controllable repair mechanism to guarantee identical net pairs from two lines is presented: i. repairs the identical yet conflict nets after the duplication (copy & paste) from original rail to complementary rail, and ii. repairs the non-identical nets in off-the-stock DPL circuits; These rerouting steps are carried out starting from a placed and routed netlist using Xilinx Description Language (XDL). Low level XDL modifications have been completely automated using a set of APIs named RapidSmith. Experimental EM attacks show that the resistance level of an AES core after the automatic routing repair is increased in a factor of at least 3.5. Timing analyses further demonstrate that net delay differences between complementary networks are minimized significantly.

More information

Item ID: 20892
DC Identifier: http://oa.upm.es/20892/
OAI Identifier: oai:oa.upm.es:20892
Official URL: http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6416733
Deposited by: Memoria Investigacion
Deposited on: 19 Nov 2013 15:33
Last Modified: 22 Sep 2014 11:21
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