A Circuit Implementing Massive Parallelism in Transition P Systems.

Alonso Villaverde, Santiago; Fernández Muñoz, Luis; Arroyo Montoro, Fernando y Gil Rubio, Fco. Javier (2008). A Circuit Implementing Massive Parallelism in Transition P Systems.. "International Journal Information Technologies and Knowledge.", v. 2 (n. 1); pp. 35-42. ISSN 1313-048X.

Descripción

Título: A Circuit Implementing Massive Parallelism in Transition P Systems.
Autor/es:
  • Alonso Villaverde, Santiago
  • Fernández Muñoz, Luis
  • Arroyo Montoro, Fernando
  • Gil Rubio, Fco. Javier
Tipo de Documento: Artículo
Título de Revista/Publicación: International Journal Information Technologies and Knowledge.
Fecha: Enero 2008
Volumen: 2
Materias:
Palabras Clave Informales: Transition P System, membrane computing, circuit design.
Escuela: E.U. de Informática (UPM) [antigua denominación]
Departamento: Lenguajes, Proyectos y Sistemas Informáticos
Licencias Creative Commons: Reconocimiento - Sin obra derivada - No comercial

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Resumen

P-systems are based on biological membranes and try to emulate cell behavior and its evolution due to the presence of chemical elements. These systems perform computation through transition between two consecutive configurations, which consist in a m-tuple of multisets present at any moment in the existing m regions of the system. Transition between two configurations is performed by using evolution rules also present in each region. Among main Transition P-systems characteristics are massive parallelism and non determinism. This work is part of a very large project and tries to determine the design of a hardware circuit that can improve remarkably the process involved in the evolution of a membrane. Process in biological cells has two different levels of parallelism: the first one, obviously, is the evolution of each cell inside the whole set, and the second one is the application of the rules inside one membrane. This paper presents an evolution of the work done previously and includes an improvement that uses massive parallelism to do transition between two states. To achieve this, the initial set of rules is transformed into a new set that consists in all their possible combinations, and each of them is treated like a new rule (participant antecedents are added to generate a new multiset), converting an unique rule application in a way of parallelism in the means that several rules are applied at the same time. In this paper, we present a circuit that is able to process this kind of rules and to decode the result, taking advantage of all the potential that hardware has to implement P Systems versus previously proposed sequential solutions.

Más información

ID de Registro: 2194
Identificador DC: http://oa.upm.es/2194/
Identificador OAI: oai:oa.upm.es:2194
URL Oficial: http://www.foibg.com/ijitk/ijitk-vol02/ijitk-fv02.htm
Depositado por: Memoria Investigacion
Depositado el: 05 Feb 2010 11:28
Ultima Modificación: 24 Nov 2015 15:15
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