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A hardware mechanism to reduce the energy consumption of the register file of in-order architectures
Cita
Ayala Rodrigo, José Luis, López Vallejo, Marisa 
ORCID: https://orcid.org/0000-0002-3833-524X, López Barrio, Carlos Alberto ORCID: https://orcid.org/0000-0002-2423-5272 and Veidenbaum, Alexander
(2008).
A hardware mechanism to reduce the energy consumption of the register file of in-order architectures.
"International Journal of Embedded Systems", v. 3
(n. 4);
pp. 285-293.
ISSN 1741-1076.
https://doi.org/10.1504/IJES.2008.022400.
ORCID: https://orcid.org/0000-0002-3833-524X, López Barrio, Carlos Alberto ORCID: https://orcid.org/0000-0002-2423-5272 and Veidenbaum, Alexander
(2008).
A hardware mechanism to reduce the energy consumption of the register file of in-order architectures.
"International Journal of Embedded Systems", v. 3
(n. 4);
pp. 285-293.
ISSN 1741-1076.
https://doi.org/10.1504/IJES.2008.022400.
Descripción
| Título: | A hardware mechanism to reduce the energy consumption of the register file of in-order architectures |
|---|---|
| Autor/es: |
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| Tipo de Documento: | Artículo |
| Título de Revista/Publicación: | International Journal of Embedded Systems |
| Fecha: | Julio 2008 |
| ISSN: | 1741-1076 |
| Volumen: | 3 |
| Número: | 4 |
| Materias: | |
| ODS: | |
| Palabras Clave Informales: | register file; in-order; power reduction; predecode; hardware approach. |
| Escuela: | E.T.S.I. Telecomunicación (UPM) |
| Departamento: | Ingeniería Electrónica |
| Licencias Creative Commons: | Reconocimiento - Sin obra derivada - No comercial |
Resumen
This paper introduces an efficient hardware approach to reduce the register file energy consumption by turning unused registers into a low power state. Bypassing the register fields of the fetch instruction to the decode stage allows the identification of registers required by the current instruction (instruction predecode) and allows the control logic to turn them back on. They are put into the low-power state after the instruction use. This technique achieves an 85% energy reduction with no performance penalty.
Más información
| ID de Registro: | 2785 |
|---|---|
| Identificador DC: | https://oa.upm.es/2785/ |
| Identificador OAI: | oai:oa.upm.es:2785 |
| URL Portal Científico: | https://portalcientifico.upm.es/es/ipublic/item/5615652 |
| Identificador DOI: | 10.1504/IJES.2008.022400 |
| Depositado por: | Memoria Investigacion |
| Depositado el: | 08 Abr 2010 10:41 |
| Ultima Modificación: | 12 Nov 2025 00:00 |
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