Further Specialization of Clustered VLIW Processors: A MAP Decoder for Software Defined Radio

Ituero Herrero, Pablo and López Vallejo, Marisa (2008). Further Specialization of Clustered VLIW Processors: A MAP Decoder for Software Defined Radio. "Etri Journal", v. 30 (n. 1); pp. 113-128. ISSN 1225-6463. https://doi.org/10.4218/etrij.08.0107.0076.

Description

Title: Further Specialization of Clustered VLIW Processors: A MAP Decoder for Software Defined Radio
Author/s:
  • Ituero Herrero, Pablo
  • López Vallejo, Marisa
Item Type: Article
Título de Revista/Publicación: Etri Journal
Date: February 2008
ISSN: 1225-6463
Volume: 30
Subjects:
Freetext Keywords: Application specific instruction-set processor (ASIP), maximum a posteriori (MAP), soft-input soft-output (SISO) decoder, software defined radio (SDR), turbo code, very long instruction word (VLIW) architectures.
Faculty: E.T.S.I. Telecomunicación (UPM)
Department: Ingeniería Electrónica
Creative Commons Licenses: Recognition - No derivative works - Non commercial

Full text

[img]
Preview
PDF - Requires a PDF viewer, such as GSview, Xpdf or Adobe Acrobat Reader
Download (759kB) | Preview

Abstract

Turbo codes are extensively used in current communications standards and have a promising outlook for future generations. The advantages of software defined radio, especially dynamic reconfiguration, make it very attractive in this multi-standard scenario. However, the complex and power consuming implementation of the maximum a posteriori (MAP) algorithm, employed by turbo decoders, sets hurdles to this goal. This work introduces an ASIP architecture for the MAP algorithm, based on a dual-clustered VLIW processor. It displays the good performance of application specific designs along with the versatility of processors, which makes it compliant with leading edge standards. The machine deals with multi-operand instructions in an innovative way, the fetching and assertion of data is serialized and the addressing is automatized and transparent for the programmer. The performance-area trade-off of the proposed architecture achieves a throughput of 8 cycles per symbol with very low power dissipation.

More information

Item ID: 2786
DC Identifier: http://oa.upm.es/2786/
OAI Identifier: oai:oa.upm.es:2786
DOI: 10.4218/etrij.08.0107.0076
Official URL: http://etrij.etri.re.kr/
Deposited by: Memoria Investigacion
Deposited on: 08 Apr 2010 09:11
Last Modified: 20 Apr 2016 12:26
  • Logo InvestigaM (UPM)
  • Logo GEOUP4
  • Logo Open Access
  • Open Access
  • Logo Sherpa/Romeo
    Check whether the anglo-saxon journal in which you have published an article allows you to also publish it under open access.
  • Logo Dulcinea
    Check whether the spanish journal in which you have published an article allows you to also publish it under open access.
  • Logo de Recolecta
  • Logo del Observatorio I+D+i UPM
  • Logo de OpenCourseWare UPM