Design and Implementation of a HardwareModule for MIMO Decoding in a 4G Wireless Receiver

Jimenez-Pacheco, A. and Fernandez Herrero, Angel and Casajús Quirós, Francisco Javier (2008). Design and Implementation of a HardwareModule for MIMO Decoding in a 4G Wireless Receiver. "VLSI Design", v. 2008 ; pp. 1-8. ISSN 0020-7217. https://doi.org/10.1155/2008/312614.

Description

Title: Design and Implementation of a HardwareModule for MIMO Decoding in a 4G Wireless Receiver
Author/s:
  • Jimenez-Pacheco, A.
  • Fernandez Herrero, Angel
  • Casajús Quirós, Francisco Javier
Item Type: Article
Título de Revista/Publicación: VLSI Design
Date: 2008
ISSN: 0020-7217
Volume: 2008
Subjects:
Freetext Keywords: Hardware Module; MIMO; 4G; Wireless
Faculty: E.T.S.I. Telecomunicación (UPM)
Department: Señales, Sistemas y Radiocomunicaciones
Creative Commons Licenses: Recognition - No derivative works - Non commercial

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Abstract

Future 4th Generation (4G) wireless multiuser communication systems will have to provide advanced multimedia services to an increasing number of users, making good use of the scarce spectrum resources. Thus, 4G systemdesign should pursue both highertransmission bit rates and higher spectral efficiencies. To achieve this goal,multiple antenna systems are called to play a crucial role. In this contribution we address the implementation in FPGAs of a multiple-input multiple-output (MIMO) decoder embedded in a prototype of a 4G mobile receiver. This MIMO decoder is part of a multicarrier code-division multiple-access (MC-CDMA) radio system, equipped with multiple antennas at both ends of the link, that is able to handle up to 32 users and provides raw transmission bit-rates up to 125 Mbps. The task of the MIMO decoder is to appropriately combine the signals simultaneously received on all antennas to construct an improved signal, free of interference, from which to estimate the transmitted symbols. A comprehensive explanation of the complete design process is provided, including architectural decisions, floating-point to fixedpoint translation, and description of the validation procedure. We also report implementation results using FPGA devices of the Xilinx Virtex-4 family.

More information

Item ID: 2858
DC Identifier: http://oa.upm.es/2858/
OAI Identifier: oai:oa.upm.es:2858
DOI: 10.1155/2008/312614
Official URL: http://www.hindawi.com/journals/vlsi/
Deposited by: Memoria Investigacion
Deposited on: 13 Apr 2010 09:43
Last Modified: 20 Apr 2016 12:29
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