Texto completo
Vista Previa |
PDF (Portable Document Format)
- Se necesita un visor de ficheros PDF, como GSview, Xpdf o Adobe Acrobat Reader
Descargar (1MB) | Vista Previa |
Floating-point exponentiation units for reconfigurable computing
Cita
Dinechin, Florent de, Echeverría Aramendi, Pedro, López Vallejo, Marisa 
ORCID: https://orcid.org/0000-0002-3833-524X and Pasca, Bogdan
(2013).
Floating-point exponentiation units for reconfigurable computing.
"ACM Transactions on Reconfigurable Technology and Systems (TRETS)", v. 6
(n. 1);
pp. 1-15.
ISSN 1936-7406.
https://doi.org/10.1145/2457443.2457447.
ORCID: https://orcid.org/0000-0002-3833-524X and Pasca, Bogdan
(2013).
Floating-point exponentiation units for reconfigurable computing.
"ACM Transactions on Reconfigurable Technology and Systems (TRETS)", v. 6
(n. 1);
pp. 1-15.
ISSN 1936-7406.
https://doi.org/10.1145/2457443.2457447.
Descripción
| Título: | Floating-point exponentiation units for reconfigurable computing |
|---|---|
| Autor/es: |
|
| Tipo de Documento: | Artículo |
| Título de Revista/Publicación: | ACM Transactions on Reconfigurable Technology and Systems (TRETS) |
| Fecha: | Mayo 2013 |
| ISSN: | 1936-7406 |
| Volumen: | 6 |
| Número: | 1 |
| Materias: | |
| ODS: | |
| Palabras Clave Informales: | CCS for this Article, Hardware, Integrated circuits, Logic circuits, Arithmetic and datapath circuits |
| Escuela: | E.T.S.I. Telecomunicación (UPM) |
| Departamento: | Ingeniería Electrónica |
| Licencias Creative Commons: | Reconocimiento - Sin obra derivada - No comercial |
Resumen
The high performance and capacity of current FPGAs makes them suitable as acceleration co-processors. This article studies the implementation, for such accelerators, of the floating-point power function xy as defined by the C99 and IEEE 754-2008 standards, generalized here to arbitrary exponent and mantissa sizes. Last-bit accuracy at the smallest possible cost is obtained thanks to a careful study of the various subcomponents: a floating-point logarithm, a modified floating-point exponential, and a truncated floating-point multiplier. A parameterized architecture generator in the open-source FloPoCo project is presented in details and evaluated.
Más información
| ID de Registro: | 29552 |
|---|---|
| Identificador DC: | https://oa.upm.es/29552/ |
| Identificador OAI: | oai:oa.upm.es:29552 |
| URL Portal Científico: | https://portalcientifico.upm.es/es/ipublic/item/5488475 |
| Identificador DOI: | 10.1145/2457443.2457447 |
| URL Oficial: | http://dl.acm.org/citation.cfm?doid=2457443.245744... |
| Depositado por: | Memoria Investigacion |
| Depositado el: | 06 Jul 2014 10:16 |
| Ultima Modificación: | 12 Nov 2025 00:00 |
Acciones
- Estadísticas
- Exportar cita
- Editar (sólo personal del Archivo)
