Floating-point exponentiation units for reconfigurable computing

Dinechin, Florent de and Echeverría Aramendi, Pedro and López Vallejo, Marisa and Pasca, Bogdan (2013). Floating-point exponentiation units for reconfigurable computing. "ACM Transactions on Reconfigurable Technology and Systems (TRETS)", v. 6 (n. 1); pp. 1-15. ISSN 1936-7406. https://doi.org/10.1145/2457443.2457447.

Description

Title: Floating-point exponentiation units for reconfigurable computing
Author/s:
  • Dinechin, Florent de
  • Echeverría Aramendi, Pedro
  • López Vallejo, Marisa
  • Pasca, Bogdan
Item Type: Article
Título de Revista/Publicación: ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Date: May 2013
ISSN: 1936-7406
Volume: 6
Subjects:
Freetext Keywords: CCS for this Article, Hardware, Integrated circuits, Logic circuits, Arithmetic and datapath circuits
Faculty: E.T.S.I. Telecomunicación (UPM)
Department: Ingeniería Electrónica
Creative Commons Licenses: Recognition - No derivative works - Non commercial

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Abstract

The high performance and capacity of current FPGAs makes them suitable as acceleration co-processors. This article studies the implementation, for such accelerators, of the floating-point power function xy as defined by the C99 and IEEE 754-2008 standards, generalized here to arbitrary exponent and mantissa sizes. Last-bit accuracy at the smallest possible cost is obtained thanks to a careful study of the various subcomponents: a floating-point logarithm, a modified floating-point exponential, and a truncated floating-point multiplier. A parameterized architecture generator in the open-source FloPoCo project is presented in details and evaluated.

More information

Item ID: 29552
DC Identifier: http://oa.upm.es/29552/
OAI Identifier: oai:oa.upm.es:29552
DOI: 10.1145/2457443.2457447
Official URL: http://dl.acm.org/citation.cfm?doid=2457443.2457447
Deposited by: Memoria Investigacion
Deposited on: 06 Jul 2014 10:16
Last Modified: 21 Apr 2016 23:57
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