Explointing FPGA block memories for protected cryptographic implementations

Bhasin, Shivam; He, Wei; Guilley, Sylvain y Danger, Jean-Luc (2013). Explointing FPGA block memories for protected cryptographic implementations. En: "8th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC)", 10/07/2013 - 12/07/2013, Darmstadt, Germany. ISBN 978-1-4673-6180-4. pp. 1-5. https://doi.org/10.1109/ReCoSoC.2013.6581529.

Descripción

Título: Explointing FPGA block memories for protected cryptographic implementations
Autor/es:
  • Bhasin, Shivam
  • He, Wei
  • Guilley, Sylvain
  • Danger, Jean-Luc
Tipo de Documento: Ponencia en Congreso o Jornada (Artículo)
Título del Evento: 8th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC)
Fechas del Evento: 10/07/2013 - 12/07/2013
Lugar del Evento: Darmstadt, Germany
Título del Libro: Explointing FPGA block memories for protected cryptographic implementations
Fecha: 2013
ISBN: 978-1-4673-6180-4
Materias:
Palabras Clave Informales: FPGA, Side-Channel Analysis, Block Memories, Countermeasures
Escuela: Centro de Electrónica Industrial (CEI) (UPM)
Departamento: Otro
Licencias Creative Commons: Reconocimiento - Sin obra derivada - No comercial

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Resumen

Modern Field Programmable Gate Arrays (FPGAs) are power packed with features to facilitate designers. Availability of features like huge block memory (BRAM), Digital Signal Processing (DSP) cores, embedded CPU makes the design strategy of FPGAs quite different from ASICs. FPGA are also widely used in security-critical application where protection against known attacks is of prime importance. We focus ourselves on physical attacks which target physical implementations. To design countermeasures against such attacks, the strategy for FPGA designers should also be different from that in ASIC. The available features should be exploited to design compact and strong countermeasures. In this paper, we propose methods to exploit the BRAMs in FPGAs for designing compact countermeasures. BRAM can be used to optimize intrinsic countermeasures like masking and dual-rail logic, which otherwise have significant overhead (at least 2X). The optimizations are applied on a real AES-128 co-processor and tested for area overhead and resistance on Xilinx Virtex-5 chips. The presented masking countermeasure has an overhead of only 16% when applied on AES. Moreover Dual-rail Precharge Logic (DPL) countermeasure has been optimized to pack the whole sequential part in the BRAM, hence enhancing the security. Proper robustness evaluations are conducted to analyze the optimization for area and security.

Más información

ID de Registro: 29698
Identificador DC: http://oa.upm.es/29698/
Identificador OAI: oai:oa.upm.es:29698
Identificador DOI: 10.1109/ReCoSoC.2013.6581529
Depositado por: Memoria Investigacion
Depositado el: 27 Abr 2015 19:00
Ultima Modificación: 27 Abr 2015 19:00
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