Explointing FPGA block memories for protected cryptographic implementations

Bhasin, Shivam and He, Wei and Guilley, Sylvain and Danger, Jean-Luc (2013). Explointing FPGA block memories for protected cryptographic implementations. In: "8th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC)", 10/07/2013 - 12/07/2013, Darmstadt, Germany. ISBN 978-1-4673-6180-4. pp. 1-5. https://doi.org/10.1109/ReCoSoC.2013.6581529.

Description

Title: Explointing FPGA block memories for protected cryptographic implementations
Author/s:
  • Bhasin, Shivam
  • He, Wei
  • Guilley, Sylvain
  • Danger, Jean-Luc
Item Type: Presentation at Congress or Conference (Article)
Event Title: 8th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC)
Event Dates: 10/07/2013 - 12/07/2013
Event Location: Darmstadt, Germany
Title of Book: Explointing FPGA block memories for protected cryptographic implementations
Date: 2013
ISBN: 978-1-4673-6180-4
Subjects:
Freetext Keywords: FPGA, Side-Channel Analysis, Block Memories, Countermeasures
Faculty: Centro de Electrónica Industrial (CEI) (UPM)
Department: Otro
Creative Commons Licenses: Recognition - No derivative works - Non commercial

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Abstract

Modern Field Programmable Gate Arrays (FPGAs) are power packed with features to facilitate designers. Availability of features like huge block memory (BRAM), Digital Signal Processing (DSP) cores, embedded CPU makes the design strategy of FPGAs quite different from ASICs. FPGA are also widely used in security-critical application where protection against known attacks is of prime importance. We focus ourselves on physical attacks which target physical implementations. To design countermeasures against such attacks, the strategy for FPGA designers should also be different from that in ASIC. The available features should be exploited to design compact and strong countermeasures. In this paper, we propose methods to exploit the BRAMs in FPGAs for designing compact countermeasures. BRAM can be used to optimize intrinsic countermeasures like masking and dual-rail logic, which otherwise have significant overhead (at least 2X). The optimizations are applied on a real AES-128 co-processor and tested for area overhead and resistance on Xilinx Virtex-5 chips. The presented masking countermeasure has an overhead of only 16% when applied on AES. Moreover Dual-rail Precharge Logic (DPL) countermeasure has been optimized to pack the whole sequential part in the BRAM, hence enhancing the security. Proper robustness evaluations are conducted to analyze the optimization for area and security.

More information

Item ID: 29698
DC Identifier: http://oa.upm.es/29698/
OAI Identifier: oai:oa.upm.es:29698
DOI: 10.1109/ReCoSoC.2013.6581529
Deposited by: Memoria Investigacion
Deposited on: 27 Apr 2015 19:00
Last Modified: 27 Apr 2015 19:00
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