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Virtual Architectures for Partial Runtime Reconfigurable Systems. Application to Network on Chip based SoC Emulation
Cita
Esteves Krasteva, Yana, Torre Arnanz, Eduardo de la 
ORCID: https://orcid.org/0000-0001-5697-0573 and Riesgo Alcaide, Teresa ORCID: https://orcid.org/0000-0003-0532-8681
(2008).
Virtual Architectures for Partial Runtime Reconfigurable Systems. Application to Network on Chip based SoC Emulation.
En: "34th Annual Conference of the IEEE Industrial Electronics Society. IECON-2008", 10/11/2008-13/11/2008, Orlando, Florida, USA. ISBN 978-1-4244-1766-7. pp..
ORCID: https://orcid.org/0000-0001-5697-0573 and Riesgo Alcaide, Teresa ORCID: https://orcid.org/0000-0003-0532-8681
(2008).
Virtual Architectures for Partial Runtime Reconfigurable Systems. Application to Network on Chip based SoC Emulation.
En: "34th Annual Conference of the IEEE Industrial Electronics Society. IECON-2008", 10/11/2008-13/11/2008, Orlando, Florida, USA. ISBN 978-1-4244-1766-7. pp..
Descripción
| Título: | Virtual Architectures for Partial Runtime Reconfigurable Systems. Application to Network on Chip based SoC Emulation |
|---|---|
| Autor/es: |
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| Tipo de Documento: | Ponencia en Congreso o Jornada (Artículo) |
| Título del Evento: | 34th Annual Conference of the IEEE Industrial Electronics Society. IECON-2008 |
| Fechas del Evento: | 10/11/2008-13/11/2008 |
| Lugar del Evento: | Orlando, Florida, USA |
| Título del Libro: | Industrial Electronics, 2008. IECON 2008. 34th Annual Conference of IEEE |
| Fecha: | 2008 |
| ISBN: | 978-1-4244-1766-7 |
| Materias: | |
| ODS: | |
| Escuela: | E.T.S.I. Industriales (UPM) |
| Departamento: | Automática, Ingeniería Electrónica e Informática Industrial [hasta 2014] |
| Licencias Creative Commons: | Reconocimiento - Sin obra derivada - No comercial |
Resumen
The paper presents a method for designing Virtual Architectures (VAs) for partial runtime reconfigurable systems (pRTRs). The presented method permits to create flexible pRTRs. Such pRTR system is used as a core for a Network on Chip based SoC emulation. The main advantage of the emulation framework is that it permits fast emulation and design space exploration. The paper includes a brief description of all the building elements of the emulation framework and a use case that demonstrates the advantages of the designed pRTRs.
Más información
| ID de Registro: | 3406 |
|---|---|
| Identificador DC: | https://oa.upm.es/3406/ |
| Identificador OAI: | oai:oa.upm.es:3406 |
| URL Oficial: | http://iecon2008.auburn.edu/index.html |
| Depositado por: | Memoria Investigacion |
| Depositado el: | 22 Jun 2010 08:51 |
| Ultima Modificación: | 20 Abr 2016 12:56 |
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