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Algorithms hardware implementation for ultrasonic data processing in SHM system
Cita
Alonso Alegre, Javier, García Corcuera, Adolfo, Aranguren Aramendia, Gerardo, Monje, Pedro María, Alcaide Pardo, Ángel, Ruiz González, Mariano 
ORCID: https://orcid.org/0000-0002-1337-0110 and Barrera López de Turiso, Eduardo ORCID: https://orcid.org/0000-0001-7197-8821
(2014).
Algorithms hardware implementation for ultrasonic data processing in SHM system.
En: "7th European Workshop on Structural Health Monitoring (EWSHM 2014)", 8/07/2014 - 11/07/2014, Nantes, France. pp. 858-865.
ORCID: https://orcid.org/0000-0002-1337-0110 and Barrera López de Turiso, Eduardo ORCID: https://orcid.org/0000-0001-7197-8821
(2014).
Algorithms hardware implementation for ultrasonic data processing in SHM system.
En: "7th European Workshop on Structural Health Monitoring (EWSHM 2014)", 8/07/2014 - 11/07/2014, Nantes, France. pp. 858-865.
Descripción
| Título: | Algorithms hardware implementation for ultrasonic data processing in SHM system |
|---|---|
| Autor/es: |
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| Tipo de Documento: | Ponencia en Congreso o Jornada (Artículo) |
| Título del Evento: | 7th European Workshop on Structural Health Monitoring (EWSHM 2014) |
| Fechas del Evento: | 8/07/2014 - 11/07/2014 |
| Lugar del Evento: | Nantes, France |
| Título del Libro: | 7th European Workshop on Structural Health Monitoring |
| Fecha: | 2014 |
| Materias: | |
| ODS: | |
| Palabras Clave Informales: | Hardware algorithms, FPGA, beamforming, signal characterization. |
| Escuela: | E.T.S.I. y Sistemas de Telecomunicación (UPM) |
| Departamento: | Ingeniería Telemática y Electrónica |
| Licencias Creative Commons: | Reconocimiento - Sin obra derivada - No comercial |
Resumen
Nowadays, devices that monitor the health of structures consume a lot of power and need a lot of time to acquire, process, and send the information about the structure to the main processing unit. To decrease this time, fast electronic devices are starting to be used to accelerate this processing. In this paper some hardware algorithms implemented in an electronic logic programming device are described. The goal of this implementation is accelerate the process and diminish the information that has to be send. By reaching this goal, the time the processor needs for treating all the information is reduced and so the power consumption is reduced too.
Proyectos asociados
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Responsable
Título
Gobierno de España
PROSAVE2-CENIT
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Más información
| ID de Registro: | 37482 |
|---|---|
| Identificador DC: | https://oa.upm.es/37482/ |
| Identificador OAI: | oai:oa.upm.es:37482 |
| URL Oficial: | http://www.ewshm2014.com/ |
| Depositado por: | Memoria Investigacion |
| Depositado el: | 29 Mar 2016 18:07 |
| Ultima Modificación: | 29 Mar 2016 18:07 |
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