Bitslice software implementation of KeeLoq as a side-channel countermeasure

Malagón Marzo, Pedro José and Goyeneche, Juan Mariano de and Fraga Aydillo, David and Moya Fernández, José Manuel (2015). Bitslice software implementation of KeeLoq as a side-channel countermeasure. In: "Workshop on Embedded Systems Security (WESS'15)", 04/10/2015 - 09/10/2015, Amsterdam, Netherlands. https://doi.org/10.1145/2818362.2818366.

Description

Title: Bitslice software implementation of KeeLoq as a side-channel countermeasure
Author/s:
  • Malagón Marzo, Pedro José
  • Goyeneche, Juan Mariano de
  • Fraga Aydillo, David
  • Moya Fernández, José Manuel
Item Type: Presentation at Congress or Conference (Article)
Event Title: Workshop on Embedded Systems Security (WESS'15)
Event Dates: 04/10/2015 - 09/10/2015
Event Location: Amsterdam, Netherlands
Title of Book: Workshop on Embedded Systems Security (WESS'15)
Date: 2015
Subjects:
Freetext Keywords: SCA, CPA, bitslice, NLFSR, KeeLoq, ANF
Faculty: E.T.S.I. Telecomunicación (UPM)
Department: Ingeniería Electrónica
Creative Commons Licenses: Recognition - No derivative works - Non commercial

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Abstract

Bitslice is a non-conventional way to implement algorithms using a scalar processor as a {SIMD}. It involves breaking down the algorithm into logical bit operations so that N parallel <operations are possible on a single N-bit microprocessor. It is applied to encryption algorithms, processing N consecutive blocks simultaneously, to achieve high throughput. Security applications using the {KeeLoq} algorithm are not suitable to traditional bitslice implementations because usually there are no N blocks to be processed. We propose a {KeeLoq} bitslice implementation, derived from its Algebraic Normal Form, for a single input block as a countermeasure against side-channel attacks. Our experimental results show there is no timing information leaked with an improvement factor of 3.01 in executed cycles. However, the implementation is still vulnerable to differential side-channel analysis, so we propose a secured variation that increases the resistance against differential power analysis without timing leakage, with a lower improvement factor of 1.21 in executed cycles.

Funding Projects

TypeCodeAcronymLeaderTitle
Government of SpainTEC-2012-33892UnspecifiedUnspecifiedTECNOLOGIAS HW/SW PARA LA EFICIENCIA ENERGETICA EN SISTEMAS DE COMPUTACION DISTRIBUIDOS
Government of SpainRTC-2014-2717-3UnspecifiedUnspecifiedOPTIMIZACIÓN ENERGÉTICA DE CENTROS DE DATOS DE INFRAESTRUCTURAS CLOUD BASADAS EN OPENSTACK
Government of SpainIPT-2012-1041-430000RECOPUBLIUnspecifiedRed Cooperativa e interactiva de PUBLIcidad digital dotada de sistemas de gestión de medios

More information

Item ID: 42749
DC Identifier: http://oa.upm.es/42749/
OAI Identifier: oai:oa.upm.es:42749
DOI: 10.1145/2818362.2818366
Deposited by: Memoria Investigacion
Deposited on: 04 Sep 2016 08:09
Last Modified: 04 Sep 2016 08:09
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