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ORCID: https://orcid.org/0000-0002-8167-508X, Goyeneche, Juan Mariano de, Fraga Aydillo, David and Moya Fernández, José Manuel
ORCID: https://orcid.org/0000-0003-4433-2296
(2015).
Bitslice software implementation of KeeLoq as a side-channel countermeasure.
En: "Workshop on Embedded Systems Security (WESS'15)", 04/10/2015 - 09/10/2015, Amsterdam, Netherlands.
https://doi.org/10.1145/2818362.2818366.
| Título: | Bitslice software implementation of KeeLoq as a side-channel countermeasure |
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| Autor/es: |
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| Tipo de Documento: | Ponencia en Congreso o Jornada (Artículo) |
| Título del Evento: | Workshop on Embedded Systems Security (WESS'15) |
| Fechas del Evento: | 04/10/2015 - 09/10/2015 |
| Lugar del Evento: | Amsterdam, Netherlands |
| Título del Libro: | Workshop on Embedded Systems Security (WESS'15) |
| Fecha: | 2015 |
| Materias: | |
| ODS: | |
| Palabras Clave Informales: | SCA, CPA, bitslice, NLFSR, KeeLoq, ANF |
| Escuela: | E.T.S.I. Telecomunicación (UPM) |
| Departamento: | Ingeniería Electrónica |
| Licencias Creative Commons: | Reconocimiento - Sin obra derivada - No comercial |
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Bitslice is a non-conventional way to implement algorithms using a scalar processor as a {SIMD}. It involves breaking down the algorithm into logical bit operations so that N parallel <operations are possible on a single N-bit microprocessor. It is applied to encryption algorithms, processing N consecutive blocks simultaneously, to achieve high throughput. Security applications using the {KeeLoq} algorithm are not suitable to traditional bitslice implementations because usually there are no N blocks to be processed. We propose a {KeeLoq} bitslice implementation, derived from its Algebraic Normal Form, for a single input block as a countermeasure against side-channel attacks. Our experimental results show there is no timing information leaked with an improvement factor of 3.01 in executed cycles. However, the implementation is still vulnerable to differential side-channel analysis, so we propose a secured variation that increases the resistance against differential power analysis without timing leakage, with a lower improvement factor of 1.21 in executed cycles.
| ID de Registro: | 42749 |
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| Identificador DC: | https://oa.upm.es/42749/ |
| Identificador OAI: | oai:oa.upm.es:42749 |
| Identificador DOI: | 10.1145/2818362.2818366 |
| Depositado por: | Memoria Investigacion |
| Depositado el: | 04 Sep 2016 08:09 |
| Ultima Modificación: | 04 Sep 2016 08:09 |
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