Reconfiguring Crypto Hardware Accelerators on Wireless Sensor Nodes

Steffen, Peter and Oliver, Stecklina and Portilla Berrueco, Jorge and Torre Arnanz, Eduardo de la and Langendörfer, Peter and Riesgo Alcaide, Teresa (2009). Reconfiguring Crypto Hardware Accelerators on Wireless Sensor Nodes. In: "6th Annual IEEE Communications Society Conference on Sensor, Mesh and Ad Hoc Communications and Networks Workshops, 2009. SECON Workshops '09", 22/06/2009 - 26/06/2009, Roma, Italia. ISBN 978-1-4244-3938-6.

Description

Title: Reconfiguring Crypto Hardware Accelerators on Wireless Sensor Nodes
Author/s:
  • Steffen, Peter
  • Oliver, Stecklina
  • Portilla Berrueco, Jorge
  • Torre Arnanz, Eduardo de la
  • Langendörfer, Peter
  • Riesgo Alcaide, Teresa
Item Type: Presentation at Congress or Conference (Article)
Event Title: 6th Annual IEEE Communications Society Conference on Sensor, Mesh and Ad Hoc Communications and Networks Workshops, 2009. SECON Workshops '09
Event Dates: 22/06/2009 - 26/06/2009
Event Location: Roma, Italia
Title of Book: Proceedings of 6th Annual IEEE Communications Society Conference on Sensor, Mesh and Ad Hoc Communications and Networks Workshops, 2009. SECON Workshops '09
Date: July 2009
ISBN: 978-1-4244-3938-6
Subjects:
Freetext Keywords: Elliptic curve cryptography, FPGA, Reconfigurability, wireless sensor nodes
Faculty: E.T.S.I. Industriales (UPM)
Department: Automática, Ingeniería Electrónica e Informática Industrial [hasta 2014]
Creative Commons Licenses: Recognition - No derivative works - Non commercial

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Abstract

Running strong cryptographic algorithms on wireless sensor nodes is extremely difficult due to their limited resources. Hardware accelerators are a suitable means to speed up the computation and reduce power consumption. The drawback of crypto ASICs is the loss of flexibility. In this paper we will shortly introduce a modular design of elliptic curve accelerators which allows to be adjusted to several NIST recommended curves by replacing its reduction unit. This partial reconfiguration will be executed on a Spartan 3 FPGA. The visualization will be done in the following way. Standard motes will be connected to the FPG. On the motes the algorithms will be executed in software. Switching between ECC with a long key, i.e. 571 bit and those with short key length, e.g. to a key length of 163 bit, has a remarkable effect on the execution time. En-/decrypting messages sent to and received from the motes at the FPGA will show that ECC implementation has been reconfigured according to the selected curve on the motes

More information

Item ID: 5509
DC Identifier: http://oa.upm.es/5509/
OAI Identifier: oai:oa.upm.es:5509
Official URL: http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=5172959&tag=1
Deposited by: Memoria Investigacion
Deposited on: 20 Dec 2010 09:16
Last Modified: 20 Apr 2016 14:17
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