Reconfiguring Crypto Hardware Accelerators on Wireless Sensor Nodes

Steffen, Peter; Oliver, Stecklina; Portilla Berrueco, Jorge; Torre Arnanz, Eduardo de la; Langendörfer, Peter y Riesgo Alcaide, Teresa (2009). Reconfiguring Crypto Hardware Accelerators on Wireless Sensor Nodes. En: "6th Annual IEEE Communications Society Conference on Sensor, Mesh and Ad Hoc Communications and Networks Workshops, 2009. SECON Workshops '09", 22/06/2009 - 26/06/2009, Roma, Italia. ISBN 978-1-4244-3938-6.

Descripción

Título: Reconfiguring Crypto Hardware Accelerators on Wireless Sensor Nodes
Autor/es:
  • Steffen, Peter
  • Oliver, Stecklina
  • Portilla Berrueco, Jorge
  • Torre Arnanz, Eduardo de la
  • Langendörfer, Peter
  • Riesgo Alcaide, Teresa
Tipo de Documento: Ponencia en Congreso o Jornada (Artículo)
Título del Evento: 6th Annual IEEE Communications Society Conference on Sensor, Mesh and Ad Hoc Communications and Networks Workshops, 2009. SECON Workshops '09
Fechas del Evento: 22/06/2009 - 26/06/2009
Lugar del Evento: Roma, Italia
Título del Libro: Proceedings of 6th Annual IEEE Communications Society Conference on Sensor, Mesh and Ad Hoc Communications and Networks Workshops, 2009. SECON Workshops '09
Fecha: Julio 2009
ISBN: 978-1-4244-3938-6
Materias:
Palabras Clave Informales: Elliptic curve cryptography, FPGA, Reconfigurability, wireless sensor nodes
Escuela: E.T.S.I. Industriales (UPM)
Departamento: Automática, Ingeniería Electrónica e Informática Industrial [hasta 2014]
Licencias Creative Commons: Reconocimiento - Sin obra derivada - No comercial

Texto completo

[img]
Vista Previa
PDF (Document Portable Format) - Se necesita un visor de ficheros PDF, como GSview, Xpdf o Adobe Acrobat Reader
Descargar (310kB) | Vista Previa

Resumen

Running strong cryptographic algorithms on wireless sensor nodes is extremely difficult due to their limited resources. Hardware accelerators are a suitable means to speed up the computation and reduce power consumption. The drawback of crypto ASICs is the loss of flexibility. In this paper we will shortly introduce a modular design of elliptic curve accelerators which allows to be adjusted to several NIST recommended curves by replacing its reduction unit. This partial reconfiguration will be executed on a Spartan 3 FPGA. The visualization will be done in the following way. Standard motes will be connected to the FPG. On the motes the algorithms will be executed in software. Switching between ECC with a long key, i.e. 571 bit and those with short key length, e.g. to a key length of 163 bit, has a remarkable effect on the execution time. En-/decrypting messages sent to and received from the motes at the FPGA will show that ECC implementation has been reconfigured according to the selected curve on the motes

Más información

ID de Registro: 5509
Identificador DC: http://oa.upm.es/5509/
Identificador OAI: oai:oa.upm.es:5509
URL Oficial: http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=5172959&tag=1
Depositado por: Memoria Investigacion
Depositado el: 20 Dic 2010 09:16
Ultima Modificación: 20 Abr 2016 14:17
  • Open Access
  • Open Access
  • Sherpa-Romeo
    Compruebe si la revista anglosajona en la que ha publicado un artículo permite también su publicación en abierto.
  • Dulcinea
    Compruebe si la revista española en la que ha publicado un artículo permite también su publicación en abierto.
  • Recolecta
  • e-ciencia
  • Observatorio I+D+i UPM
  • OpenCourseWare UPM