Using Partial Reconfiguration for SoC Design and Implementation

Esteves Krasteva, Yana; Portilla Berrueco, Jorge; Tobajas Guerrero, Felix y Torre Arnanz, Eduardo de la (2009). Using Partial Reconfiguration for SoC Design and Implementation. En: "VLSI Circuits and Systems IV", 01/05/2009 - 03/05/2009, Dresden, Alemania. ISBN 9780819476371.

Descripción

Título: Using Partial Reconfiguration for SoC Design and Implementation
Autor/es:
  • Esteves Krasteva, Yana
  • Portilla Berrueco, Jorge
  • Tobajas Guerrero, Felix
  • Torre Arnanz, Eduardo de la
Tipo de Documento: Ponencia en Congreso o Jornada (Artículo)
Título del Evento: VLSI Circuits and Systems IV
Fechas del Evento: 01/05/2009 - 03/05/2009
Lugar del Evento: Dresden, Alemania
Título del Libro: Proceedings of VLSI Circuits and Systems IV
Fecha: Mayo 2009
ISBN: 9780819476371
Volumen: 7363
Materias:
Escuela: E.T.S.I. Industriales (UPM)
Departamento: Automática, Ingeniería Electrónica e Informática Industrial [hasta 2014]
Licencias Creative Commons: Reconocimiento - Sin obra derivada - No comercial

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Resumen

Most reconfigurable systems rely on FPGA technology. Among these ones, those which permit dynamic and partial reconfiguration, offer added benefits in flexibility, in-field device upgrade, improved design and manufacturing time, and even, in some cases, power consumption reductions. However, dynamic reconfiguration is a complex task, and the real benefits of its use in real applications have been often questioned. This paper presents an overview of the partial reconfiguration technique application, along with four original applications. The main goal of these applications is to test several architectures with different flexibility and, to search for the partial reconfiguration "killing application", that is, the application that better demonstrates the benefits of today reconfigurable systems based on commercial FPGAs. Therefore, the presented applications are rather a proof of concept, than fully operative and closed systems. First, a brief introduction to the partial reconfigurable systems application topic has been included. After that, the descriptions of the created reconfigurable systems are presented: first, an on-chip communications emulation framework, second, an on chip debugging system, third, a wireless sensor network reconfigurable node and finally, a remote reconfigurable client-server device. Each application is described in a separate section of the paper along with some test and results. General conclusions are included at the end of the paper

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ID de Registro: 5511
Identificador DC: http://oa.upm.es/5511/
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Depositado por: Memoria Investigacion
Depositado el: 20 Dic 2010 11:13
Ultima Modificación: 18 Abr 2016 06:33
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