Reducing the LSQ and L1 Data Cache Power Consuption

Apolloni, Rubén and Carazo Minguela, Pablo and Castro, Fernando and Chaver, Daniel and Pinuel, Luis and Tirado, Francisco (2010). Reducing the LSQ and L1 Data Cache Power Consuption. In: "CACIC 2010 - XVI Congreso Argentino de Ciencias de la Computación", 18/10/2010 - 22/10/2010, Buenos Aires, Argentina.

Description

Title: Reducing the LSQ and L1 Data Cache Power Consuption
Author/s:
  • Apolloni, Rubén
  • Carazo Minguela, Pablo
  • Castro, Fernando
  • Chaver, Daniel
  • Pinuel, Luis
  • Tirado, Francisco
Item Type: Presentation at Congress or Conference (Article)
Event Title: CACIC 2010 - XVI Congreso Argentino de Ciencias de la Computación
Event Dates: 18/10/2010 - 22/10/2010
Event Location: Buenos Aires, Argentina
Title of Book: Actas del CACIC 2010 - XVI Congreso Argentino de Ciencias de la Computación
Date: 2010
Subjects:
Faculty: E.U. de Informática (UPM)
Department: Informática Aplicada [hasta 2014]
Creative Commons Licenses: Recognition - No derivative works - Non commercial

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Abstract

In most modern processor designs, the HW dedicated to store data and instructions (memory hierarchy) has become a major consumer of power. In order to reduce this power consumption, we propose in this paper two techniques, one to filter accesses to the LSQ (Load-Store Queue) based on both timing and address information, and the other to filter accesses to the first level data cache based on a forwarding predictor. Our simulation results show that the power consumption decreases in 30-40% in each structure, with a negligible performance penalty of less than 0.1%.

More information

Item ID: 9393
DC Identifier: http://oa.upm.es/9393/
OAI Identifier: oai:oa.upm.es:9393
Deposited by: Memoria Investigacion
Deposited on: 11 Nov 2011 08:32
Last Modified: 20 Apr 2016 17:49
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