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ORCID: https://orcid.org/0000-0003-0532-8681 and Torroja Fungairiño, Yago
ORCID: https://orcid.org/0000-0002-3557-3787
(2009).
Disjoint Region Partitioning for Probabilistic Switching Activity Estimation at Register Transfer Level.
En: "18th International Workshop on Power and Timing Modeling, Optimization and Simulation", 10/09/2008-12/09/2008, Lisboa (Portugal). ISBN 978-3-540-95947-2. pp..
| Título: | Disjoint Region Partitioning for Probabilistic Switching Activity Estimation at Register Transfer Level |
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| Autor/es: |
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| Tipo de Documento: | Ponencia en Congreso o Jornada (Artículo) |
| Título del Evento: | 18th International Workshop on Power and Timing Modeling, Optimization and Simulation |
| Fechas del Evento: | 10/09/2008-12/09/2008 |
| Lugar del Evento: | Lisboa (Portugal) |
| Título del Libro: | Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation |
| Fecha: | 2009 |
| ISBN: | 978-3-540-95947-2 |
| Volumen: | XIII |
| Materias: | |
| ODS: | |
| Palabras Clave Informales: | Switching activity, CAD, RTL, BDD, activity estimation, digital circuit design, VHDL, circuit partition, power estimation. |
| Escuela: | E.T.S.I. Industriales (UPM) |
| Departamento: | Automática, Ingeniería Electrónica e Informática Industrial [hasta 2014] |
| Licencias Creative Commons: | Reconocimiento - Sin obra derivada - No comercial |
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This paper presents a partition method for probabilistic switching activity estimation of combinational circuits described at register transfer level (RTL). Probabilistic estimation of switching activity requires large and complex models that could be unfeasible for large circuits; therefore, circuit partitioning becomes a necessary step to address the analysis. Nevertheless, partition methods imply approximations that produce inaccurate results. We present a partition method based on disjoint signals that minimizes the error and, in addition, it is easy to carry out. Results show important reductions on the binary decision diagrams (BDD) of the probabilistic model as well as low errors. Furthermore, the BDD reduction ratio shows a tendency to increase with large circuits; whilst error seems to decrease with the circuit size.
| ID de Registro: | 3354 |
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| Identificador DC: | https://oa.upm.es/3354/ |
| Identificador OAI: | oai:oa.upm.es:3354 |
| URL Oficial: | http://www.springer.com/computer/hardware/book/978... |
| Depositado por: | Memoria Investigacion |
| Depositado el: | 17 Jun 2010 09:14 |
| Ultima Modificación: | 20 Abr 2016 12:54 |
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