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Efficient Implementation of Complex Multipliers on FPGAs Using DSP Slices
Cita
Paz Mongil, Pedro 
ORCID: https://orcid.org/0000-0002-9461-8906 and Garrido Gálvez, Mario ORCID: https://orcid.org/0000-0001-5739-3544
(2023).
Efficient Implementation of Complex Multipliers on FPGAs Using DSP Slices.
"Journal of Signal Processing Systems", v. 95
;
pp. 543-550.
ISSN 19398115.
https://doi.org/10.1007/s11265-023-01867-7.
ORCID: https://orcid.org/0000-0002-9461-8906 and Garrido Gálvez, Mario ORCID: https://orcid.org/0000-0001-5739-3544
(2023).
Efficient Implementation of Complex Multipliers on FPGAs Using DSP Slices.
"Journal of Signal Processing Systems", v. 95
;
pp. 543-550.
ISSN 19398115.
https://doi.org/10.1007/s11265-023-01867-7.
Descripción
| Título: | Efficient Implementation of Complex Multipliers on FPGAs Using DSP Slices |
|---|---|
| Autor/es: |
|
| Tipo de Documento: | Artículo |
| Título de Revista/Publicación: | Journal of Signal Processing Systems |
| Fecha: | 27 Abril 2023 |
| ISSN: | 19398115 |
| Volumen: | 95 |
| Materias: | |
| ODS: | |
| Palabras Clave Informales: | Complex multiplier, FPGA, rotator, FFT, DSP slice |
| Escuela: | E.T.S.I. Telecomunicación (UPM) |
| Departamento: | Ingeniería Electrónica |
| Grupo Investigación UPM: | Laboratorio de Sistemas Integrados LSI |
| Licencias Creative Commons: | Reconocimiento - No comercial |
Resumen
In this paper, we propose two efficient implementations of complex multipliers on field-programmable gate arrays (FPGAs) using DSP slices. The first implementation aims for high throughput and the second one for low area.
By mapping these circuits to the DSP slices in the FPGA, the proposed implementations have the advantage that they only require three DSP slices. Experimental results show that the proposed high-throughput implementation saves hardware resources with respect to previous approaches, while reaching the highest achievable clock frequency. Alternatively, the proposed low-area implementation reduces the amount of hardware resources even further at the cost of reducing the clock frequency.
Proyectos asociados
Tipo
Código
Acrónimo
Responsable
Título
Comunidad de Madrid
APOYO-JOVENES-21-TL23SB-116-I4FOMC
Sin especificar
Mario Garrido
FPGA Implementation of Data-Intensive Algorithms:
Neural Networks and FFT
Más información
| ID de Registro: | 75473 |
|---|---|
| Identificador DC: | https://oa.upm.es/75473/ |
| Identificador OAI: | oai:oa.upm.es:75473 |
| URL Portal Científico: | https://portalcientifico.upm.es/es/ipublic/item/10041725 |
| Identificador DOI: | 10.1007/s11265-023-01867-7 |
| URL Oficial: | https://link.springer.com/article/10.1007/s11265-0... |
| Depositado por: | Dr. Mario Garrido Gálvez |
| Depositado el: | 28 Jul 2023 14:27 |
| Ultima Modificación: | 12 Nov 2025 00:00 |
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