Texto completo
![[thumbnail of A_5_2_GSps_8_Parallel_1024_Point_MDC_FFT.pdf]](https://oa.upm.es/style/images/fileicons/application_pdf.png) |
PDF (Portable Document Format)
- Se necesita un visor de ficheros PDF, como GSview, Xpdf o Adobe Acrobat Reader
Descargar (380kB) |
A 5.2-GS/s 8-Parallel 1024-Point MDC FFT
Cita
Paz Mongil, Pedro 
ORCID: https://orcid.org/0000-0002-9461-8906 and Garrido Gálvez, Mario ORCID: https://orcid.org/0000-0001-5739-3544
(2023).
A 5.2-GS/s 8-Parallel 1024-Point MDC FFT.
En: "38th Conference on Design of Circuits and Integrated Systems (DCIS)", 15-17 November 2023, Málaga, Spain. ISBN 979-8-3503-0385-8. pp. 55-60.
https://doi.org/10.1109/DCIS58620.2023.10335965.
ORCID: https://orcid.org/0000-0002-9461-8906 and Garrido Gálvez, Mario ORCID: https://orcid.org/0000-0001-5739-3544
(2023).
A 5.2-GS/s 8-Parallel 1024-Point MDC FFT.
En: "38th Conference on Design of Circuits and Integrated Systems (DCIS)", 15-17 November 2023, Málaga, Spain. ISBN 979-8-3503-0385-8. pp. 55-60.
https://doi.org/10.1109/DCIS58620.2023.10335965.
Descripción
| Título: | A 5.2-GS/s 8-Parallel 1024-Point MDC FFT |
|---|---|
| Autor/es: |
|
| Tipo de Documento: | Ponencia en Congreso o Jornada (Artículo) |
| Título del Evento: | 38th Conference on Design of Circuits and Integrated Systems (DCIS) |
| Fechas del Evento: | 15-17 November 2023 |
| Lugar del Evento: | Málaga, Spain |
| Título del Libro: | 38th Conference on Design of Circuits and Integrated Systems (DCIS) |
| Fecha: | Noviembre 2023 |
| ISBN: | 979-8-3503-0385-8 |
| Materias: | |
| ODS: | |
| Palabras Clave Informales: | Fast Fourier transform (FFT), multi-path delay commutator (MDC), pipelined architecture. |
| Escuela: | E.T.S.I. Telecomunicación (UPM) |
| Departamento: | Ingeniería Electrónica |
| Grupo Investigación UPM: | Laboratorio de Sistemas Integrados LSI |
| Licencias Creative Commons: | Reconocimiento - No comercial |
Resumen
This paper presents an efficient 8-parallel 1024-point multi-path delay commutator (MDC) fast Fourier transform (FFT) implementation on a field-programmable gate array (FPGA). The selection of the FFT algorithm and the data orders allow for obtaining an architecture with 23 non-trivial rotators, which is the minimum number achieved so far. Additionally, the non-general rotators in the architecture are trivial rotators, constant rotators, and 1-rots, which require very few resources to be implemented. The deep pipelining in the architecture allows for reaching a throughput of 5.2 GS/s.
Proyectos asociados
Tipo
Código
Acrónimo
Responsable
Título
Comunidad de Madrid
APOYO-JOVENES-21-TL23SB-116-I4FOMC
Sin especificar
Mario Garrido
FPGA Implementation of Data-Intensive Algorithms: Neural Networks and FFT
Más información
| ID de Registro: | 77136 |
|---|---|
| Identificador DC: | https://oa.upm.es/77136/ |
| Identificador OAI: | oai:oa.upm.es:77136 |
| Identificador DOI: | 10.1109/DCIS58620.2023.10335965 |
| URL Oficial: | https://ieeexplore.ieee.org/document/10335965 |
| Depositado por: | Dr. Mario Garrido Gálvez |
| Depositado el: | 11 Ene 2024 06:45 |
| Ultima Modificación: | 11 Ene 2024 06:45 |
Acciones
- Estadísticas
- Exportar cita
- Editar (sólo personal del Archivo)
