Exploration of RISC-V architectures and extensions for hardware-accelerated post-quantum cryptography schemes on FPGAs

Resumen

The following master thesis project aims to integrate a hardware post-quantum cryptography accelerator inside an open source RISC-V extendable hardware platform, using Verilog andSystemVerilog Hardware Description Languages (HDLs). The base open source platform consists of a soft-core microcontroller with RISC-V architecture, developed by OpenHWGroup, which was designed to be extended with custom hardware of any kind and implemented in some specific commercial Field Programmable Gate Arrays (FPGAs).

This platform provides a set of hardware interfaces and implementation features that allow the user to explore different posibilities about how to integrate external hardware modules, taking into account up-and-coming RISC-V architecture characteristics and posibilities. Hence, the main contributions of this project will reside in developing, designing, simulating and implementing custom RISC-V architecture extensions with the main microcontroller, for the particular case of a hardware post-quantum cryptography accelerator. The whole integration will result in a full embedded system for FPGAs.