Design of parallel pipelined FFT architectures for 6G on FPGAs

Resumen

The goal of this Master's Thesis is the design of a parallel pipelined fast Fourier transform (FFT) architecture with reduced area and low power consumption for its implementation on field programmable gate arrays (FPGAs) for 6G applications.

To achieve this purpose, a first the research about the state of the art of the different components of an FFT and the different existing FFT architectures has been carried out.

Then, the architecture proposed in this Master's Thesis is a 1024-point radix-24 4-parallel FFT, based on existing multi-path delay feedback (MDF) architecture and a new parallel version of the single-stream feedforward (SFF) architecture, the multistream feedforward (MFF). This design is implemented on a Xilinx Virtex 7 FPGA
using VHDL. The detailed explanation of the proposed approach is presented in this Thesis, including the specific mapping on the FPGA and the different techniques used to achieve an optimized architecture implementation. Finally, the experimental results and conclusions are provided, including a comparison with other architectures
where the proposed architecture achieves low power consumption and a small usage of look-up tables (LUTs) and flip-flops (FFs) in the FPGA.