Implementation of a PCIe interface to transfer data at high speed between a host and an advanced FPGA

Resumen

One of the main bottlenecks for algorithm acceleration in hardware is data transfer between different systems. Field-programmable gait arrays (FPGAs) have several high-speed interfaces that can be used for data communication. Among them is the Peripherial Component Interconnect Express (PCIe), a serial bus that can have up to 16 parallel channels. To efficiently implement communication between a computer (Host) and an acceleration card (FPGA), it is necessary that all the elements in the chain are as fast as possible: design of the PCIe interface in the FPGA, driver support for the Operating System and application access in user space.

In this Master’s Thesis, two different projects have been implemented using two different drivers, one developed by Xilinx and the other one by CERN, so that they can be compared objectively taking into account factors such as the transfer rate achieved, the resources used in the FPGA and limitations at the level of parallelism of the structures that can be implemented to take advantage of this interface, such as a fast Fourier transform (FFT).

The obtained results reach 50% of the theoretical values in terms of transfer rate performance. Thus, the objective of implementing an interface between the computer and the FPGA through the PCIe port has been achieved, reaching values close to 80 Gbps.