Design and Development of a Test Environment for On-Board validation to test FFT architectures in a VCU128 FPGA

Resumen

In this Master’s Thesis, a fully automated on-board test environment has been designed, enabling designers to quickly test and validate their fast Fourier transform (FFT) architectures and obtain performance results in a real environment. To achieve this, a 16-channel Peripherial Component Interconnect Express (PCIe) Gen4 communication interface has been implemented between a personal computer (PC) and a field-programmable gate array (FPGA) based on the Wupper project designed by CERN.

To achieve the proposed objectives, this work incorporates a series of contributions to the original project, which are divided into hardware, high-level software and low-level software.

First, a common interface (wrapper) has been introduced for all the FFTs to be tested. Next, the necessary control mechanisms have been designed in the hardware to ensure the proper functioning of the FFTs and the synchronization of data between the two endpoints of the board used. Additionally, a system has been designed to accurately
measure the performance of the architectures, obtaining the percentage of effective clock cycles used. Regarding the low-level software, an application has been designed for data transfer and reception via direct memory access (DMA) over the PCIe interface. This application has been integrated in the high-level software to automate the test execution process. The test involves generating a series of random test vectors, transferring them to the (FPGA) where they are processed, receiving the post-processed data, and analyzing and comparing them with the expected results to validate the architecture and calculate the signal to quantization noise ratio (SQNR) of the received signal. Lastly, a script has been designed to automate the process of loading new FFT models into the board. Finally, the
designed test system is used to evaluate a state-of-the-art architecture. It is found that the test system limits the throughput of the architecture to 6.15 GB/s typically, which corresponds to approximately 20% of the PCIe rate. However, it can reach 23.18 GB/s when sending a number of bytes equal to the payload of the PCIe data transfer packets (TLP). The results are analyzed, revealing that the design of the driver used for reserving contiguous physical memory for DMA is currently the bottleneck in communication.