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A 12.8-GS/s 32-Parallel 1 Million-Point FFT
Cita
Paz Mongil, Pedro 
ORCID: https://orcid.org/0000-0002-9461-8906 and Garrido Gálvez, Mario ORCID: https://orcid.org/0000-0001-5739-3544
(2024).
A 12.8-GS/s 32-Parallel 1 Million-Point FFT.
En: "2024 39th Conference on Design of Circuits and Integrated Systems (DCIS)", 13-15 Nov 2024, Catania, Italy. ISBN 979-8-3503-6439-2. pp. 260-266.
https://doi.org/10.1109/DCIS62603.2024.10769108.
ORCID: https://orcid.org/0000-0002-9461-8906 and Garrido Gálvez, Mario ORCID: https://orcid.org/0000-0001-5739-3544
(2024).
A 12.8-GS/s 32-Parallel 1 Million-Point FFT.
En: "2024 39th Conference on Design of Circuits and Integrated Systems (DCIS)", 13-15 Nov 2024, Catania, Italy. ISBN 979-8-3503-6439-2. pp. 260-266.
https://doi.org/10.1109/DCIS62603.2024.10769108.
Descripción
| Título: | A 12.8-GS/s 32-Parallel 1 Million-Point FFT |
|---|---|
| Autor/es: |
|
| Tipo de Documento: | Ponencia en Congreso o Jornada (Artículo) |
| Título del Evento: | 2024 39th Conference on Design of Circuits and Integrated Systems (DCIS) |
| Fechas del Evento: | 13-15 Nov 2024 |
| Lugar del Evento: | Catania, Italy |
| Título del Libro: | 2024 39th Conference on Design of Circuits and Integrated Systems (DCIS) |
| Fecha: | 3 Diciembre 2024 |
| ISBN: | 979-8-3503-6439-2 |
| Materias: | |
| Palabras Clave Informales: | FFT, MDC, FPGA, parallel, pipeline, high throughput, radix-32 |
| Escuela: | E.T.S.I. Telecomunicación (UPM) |
| Departamento: | Ingeniería Electrónica |
| Grupo Investigación UPM: | Laboratorio de Sistemas Integrados LSI |
| Licencias Creative Commons: | Reconocimiento - Sin obra derivada - No comercial |
Resumen
This paper presents an FPGA-based 32-parallel 1 million-point fast Fourier transform (FFT) architecture. The proposed implementation achieves a throughput of 12.8 GSps and a latency of 84.9 μs becoming the fastest 1 million-point FFT in literature that fits in a single FPGA. Additionally, the modular design based on computing several sub-FFTs simplifies the architecture and facilitates the design, implementation, debugging, and maintenance of the proposed circuit.
Proyectos asociados
Tipo
Código
Acrónimo
Responsable
Título
Comunidad de Madrid
APOYO-JOVENES-21-TL23SB-116-I4FOMC
Sin especificar
Sin especificar
Sin especificar
Más información
| ID de Registro: | 87125 |
|---|---|
| Identificador DC: | https://oa.upm.es/87125/ |
| Identificador OAI: | oai:oa.upm.es:87125 |
| URL Portal Científico: | https://portalcientifico.upm.es/es/ipublic/item/10381054 |
| Identificador DOI: | 10.1109/DCIS62603.2024.10769108 |
| URL Oficial: | https://ieeexplore.ieee.org/abstract/document/1076... |
| Depositado por: | Pedro Paz Mongil |
| Depositado el: | 28 Ene 2025 09:20 |
| Ultima Modificación: | 15 Oct 2025 01:01 |
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