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A Serial Low-Switching FFT Architecture Specifically Tailored for Low Power Consumption
Cita
Albertuz Ribas, Francisco 
ORCID: https://orcid.org/0009-0007-0219-7299 and Garrido Gálvez, Mario ORCID: https://orcid.org/0000-0001-5739-3544
(2024).
A Serial Low-Switching FFT Architecture Specifically Tailored for Low Power Consumption.
En: "39th Conference on Design of Circuits and Integrated Systems (DCIS)", 13-15 Noviembre 2024, Catania, Italia. ISBN 979-8-3503-6439-2. pp. 1-6.
https://doi.org/10.1109/DCIS62603.2024.10769116.
ORCID: https://orcid.org/0009-0007-0219-7299 and Garrido Gálvez, Mario ORCID: https://orcid.org/0000-0001-5739-3544
(2024).
A Serial Low-Switching FFT Architecture Specifically Tailored for Low Power Consumption.
En: "39th Conference on Design of Circuits and Integrated Systems (DCIS)", 13-15 Noviembre 2024, Catania, Italia. ISBN 979-8-3503-6439-2. pp. 1-6.
https://doi.org/10.1109/DCIS62603.2024.10769116.
Descripción
| Título: | A Serial Low-Switching FFT Architecture Specifically Tailored for Low Power Consumption |
|---|---|
| Autor/es: |
|
| Tipo de Documento: | Ponencia en Congreso o Jornada (Artículo) |
| Título del Evento: | 39th Conference on Design of Circuits and Integrated Systems (DCIS) |
| Fechas del Evento: | 13-15 Noviembre 2024 |
| Lugar del Evento: | Catania, Italia |
| Título del Libro: | 39th Conference on Design of Circuits and Integrated Systems (DCIS) |
| Fecha: | 3 Diciembre 2024 |
| ISBN: | 979-8-3503-6439-2 |
| Materias: | |
| Palabras Clave Informales: | FFT, SLS, pipelined architecture, low power consumption, low switching activity, optimization, digital circuit, FPGA, 6G, radar, space, radio astronomy. |
| Escuela: | E.T.S.I. Telecomunicación (UPM) |
| Departamento: | Ingeniería Electrónica |
| Grupo Investigación UPM: | Laboratorio de Sistemas Integrados LSI |
| Licencias Creative Commons: | Reconocimiento - Sin obra derivada - No comercial |
Resumen
This paper presents a new FFT architecture called serial low-switching FFT, which has been specifically conceived for low power consumption. To achieve this, the architecture has been designed with the aim of reducing the switching activity of the components of the architecture. Experimental results show that this approach reduces the power consumption by approximately one third with respect to equivalent FFT architectures in the literature.
Proyectos asociados
Tipo
Código
Acrónimo
Responsable
Título
Gobierno de España
PID2021-126991NA-I00
RAFFTING
Mario Garrido
Realizing Advanced FFT Implementations for 6G
Gobierno de España
RYC2018-025384-I
Sin especificar
Sin especificar
Sin especificar
Más información
| ID de Registro: | 87358 |
|---|---|
| Identificador DC: | https://oa.upm.es/87358/ |
| Identificador OAI: | oai:oa.upm.es:87358 |
| URL Portal Científico: | https://portalcientifico.upm.es/es/ipublic/item/10381055 |
| Identificador DOI: | 10.1109/DCIS62603.2024.10769116 |
| URL Oficial: | https://ieeexplore.ieee.org/document/10769116 |
| Depositado por: | Francisco Albertuz Ribas |
| Depositado el: | 30 Ene 2025 10:18 |
| Ultima Modificación: | 15 Oct 2025 01:01 |
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