Performance Optimisation of Variable Precision Digital Signal Processing Algorithms

Resumen

In this Thesis we pursue a quantitative and exhaustive design effort for the logic architecture of various common Digital Signal Processing (DSP) Algorithms. First, we investigate digital architecture implementations for digital Proportional Integral Derivative (PID) controllers with precision ranging from low to high (up to 96 bit width) implemented on Xilinx Field Programmable Gate Arrays (FPGAs) with varying capabilities (Artix, Kintex, Virtex; Ultrascale, Ultrascale+), while attempting to achieve the maximum possible clock rates. We seek to develop our ability to efficiently implement systems with pipeline and feedback loops on FPGA devices that make use DSP slices (Digital Signal Processing Arithmetic Logic Units) and distributed logic simultaneously.

We take this analysis further by evaluating generic matrix multiplications of arbitrary size. We optimise our designs by minimising resources using only DSP slices and achieving maximum clock rates. Afterwards, we adapt our designs to complex numbers allowing for the parallel computation of complex matrix multiplications of generic size with variable precisions. We proceed analysing different strategies for efficient complex number multiplication.

Finally, we apply the complex-matrix multiplication algorithm to generate a recursive implementation of the Fast Fourier Transform (FFT). The previous results allow us to develop efficient FPGA implementations of parallel FFTs for a generic (power-of-r) number of points. Thanks to this example we also develop our understanding and expertise of optimising the Look Up Tables (LUTs) as distributed-logic-only implementations, as well as deepening our understanding of the synthesis and implementation tools.