Any-Radix Efficient Fully-Parallel Implementation of the Fast Fourier Transform on FPGAs

Resumen

This paper presents the results of a thorough investigation of arbitrary and mixed-radix architectures of the Fast Fourier Transform (FFT) and their efficient implementation on high performance FPGA devices. We have developed a novel methodology that recursively generates the hardware description of the logic architecture of the FFT using parameterized complex matrix multipliers. Our approach allows to easily and efficiently generate fully-parallel implementations of an arbitrary number of points. This is used for example in state-of-the-art systems with non-power-of-two number of points, such as some 6G mobile communications systems. In addition, the proposed architectures accept large amounts of pipeline to meet rigorous timing requirements. The largest implementation provided surpasses the 100 GS/s throughput threshold.