Design and Implementation of Non-Power-of-Two FFT Architectures for 5G and Beyond

Resumen

In modern communication systems, hardware architectures are used to process the fast Fourier transform (FFT), which is an essential component of the transmitters and receivers of these systems. In the new generation of 5G communication, it is established that the size of the FFTs does not need to be power-of-two. This opens the door to the possibility of processing FFTs whose size is a product of powers of two, three and five. The design of these architectures is a field that has not been explored enough to achieve a high degree of optimization, unlike architectures whose size is power-of-two, which are currently quite efficient.

In this Master Thesis, efficient pipelined FFT architectures for non-power-of-two sizes have been designed. They process serial data at a rate of one sample per clock cycle. This is achieved by reducing the number of hardware resources while maximizing the use of them.

This Master Thesis starts from previous designs of butterflies for serial processing, which are essential components of the architectures. This Master Thesis is divided in the following steps: Analyze the FFT algorithm for sizes that are non-powers-of-two, determine the input and output data orders, design the permutation circuits of the architectures, implement the architectures by connecting the butterflies and the permutation circuits, and obtain experimental results on FPGAs.

The experimental results obtained by the proposed architectures improve the power-of-two SDF FFT architectures and represents a step forward in the development of efficient architectures for FFTs used in 5G and beyond.